no test yet

2026-10-31 02:51:58 +01:00 · 2025-08-26 17:34:51 -04:00
267 changed files with 11632 additions and 8723 deletions
@@ -13,18 +13,12 @@ jobs:
                target:
                    - name: ttgo-lora32-v21
                      chip: esp32
-                    - name: ttgo-lora32-v21_GPS
-                      chip: esp32
                    - name: ttgo-lora32-v21_915
                      chip: esp32
-                    - name: ttgo-lora32-v21_915_GPS
-                      chip: esp32
                    - name: ttgo_lora32_t3s3_v1_2
                      chip: esp32s3
                    - name: heltec-lora32-v2
                      chip: esp32
-                    - name: heltec-lora32-v2_915
-                      chip: esp32
                    - name: heltec_wifi_lora_32_V3
                      chip: esp32s3
                    - name: heltec_wifi_lora_32_V3_2
@@ -35,21 +29,17 @@ jobs:
                      chip: esp32s3
                    - name: heltec_wireless_stick_lite_v3_display
                      chip: esp32s3
-                    - name: heltec_wireless_bridge
+                    - name: ESP32_DIY_LoRa
                      chip: esp32
-                    - name: ESP32_DIY_LoRa_SX1278
+                    - name: ESP32_DIY_LoRa_915
                      chip: esp32
-                    - name: ESP32_DIY_LoRa_915_SX1276
+                    - name: ESP32_DIY_1W_LoRa
                      chip: esp32
-                    - name: ESP32_DIY_1W_LoRa_E22_400M30S
+                    - name: ESP32_DIY_1W_LoRa_915
                      chip: esp32
-                    - name: ESP32_DIY_1W_LoRa_915_E22_900M30S
+                    - name: ESP32_DIY_1W_LoRa_LLCC68
                      chip: esp32
-                    - name: ESP32_DIY_1W_LoRa_E220_400M30S
-                      chip: esp32
-                    - name: ESP32_DIY_1W_LoRa_E32_400M30S
-                      chip: esp32
-                    - name: ESP32_DIY_1W_LoRa_Mesh_V1_2_E22_400M30S
+                    - name: ESP32_DIY_1W_LoRa_Mesh_V1_2
                      chip: esp32
                    - name: ttgo-t-beam-v1_2
                      chip: esp32
@@ -61,8 +51,6 @@ jobs:
                      chip: esp32
                    - name: ttgo-t-beam-v1_SX1268
                      chip: esp32
-                    - name: ttgo-t-beam-v1_SX1262
-                      chip: esp32
                    - name: ttgo-t-beam-v1_2_SX1262
                      chip: esp32
                    - name: ttgo_t_deck_plus
@@ -71,68 +59,51 @@ jobs:
                      chip: esp32s3
                    - name: ttgo_t_beam_s3_SUPREME_v3
                      chip: esp32s3
-                    - name: ESP32_DIY_LoRa_A7670_SX1278
+                    - name: ESP32_DIY_LoRa_A7670
                      chip: esp32
-                    - name: ESP32_DIY_LoRa_A7670_915_SX1276
+                    - name: ESP32_DIY_LoRa_A7670_915
                      chip: esp32
                    - name: heltec_wireless_tracker
                      chip: esp32s3
                    - name: heltec_ht-ct62
                      chip: esp32c3
-                    - name: heltec_wireless_paper_v1
-                      chip: esp32s3
-                    - name: heltec_wireless_paper_v1_2
-                      chip: esp32s3
-                    - name: heltec_vision_master_e290
+                    - name: heltec_wireless_paper
                      chip: esp32s3
                    - name: OE5HWN_MeshCom
                      chip: esp32
-                    - name: WEMOS_LOLIN32_OLED_DIY_LoRa_SX1278
+                    - name: WEMOS-LOLIN32-OLED-DIY
                      chip: esp32
-                    - name: WEMOS_D1_R32_DIY_LoRa_SX1278
+                    - name: WEMOS-D1-R32-RA02
                      chip: esp32
-                    - name: WEMOS_S2_MINI_DIY_LoRa_SX1278
+                    - name: WEMOS_S2_MINI_DIY_LoRa
                      chip: esp32s2
-                    - name: ESP32C3_DIY_1W_LoRa_E22_400M30S
+                    - name: esp32c3_DIY_1W_LoRa
                      chip: esp32c3
-                    - name: ESP32C3_DIY_1W_LoRa_915_E22_900M30S
+                    - name: esp32c3_DIY_1W_LoRa_915
                      chip: esp32c3
-                    - name: ESP32C3_OctopusLab_LoRa
-                      chip: esp32c3
-                    - name: ESP32C3_SuperMini_DIY_LoRa_SX1278
+                    - name: ESP32_C3_OctopusLab_LoRa
                      chip: esp32c3
                    - name: QRPLabs_LightGateway_1_0
                      chip: esp32s3
                    - name: QRPLabs_LightGateway_Plus_1_0
                      chip: esp32s3
-                    - name: RPC_LORA_DIGIGATE_1W
-                      chip: esp32
                    - name: XIAO_ESP32S3_WIO_SX1262
                      chip: esp32s3
-                    - name: RAK3312
-                      chip: esp32s3
-                    - name: RAK3112
-                      chip: esp32s3
                    - name: TROY_LoRa_APRS
-                      chip: esp32
-                    - name: ESP32_9M2IBR_1W_LoRa_GPS_E22_400M30S
-                      chip: esp32
+                      chip: esp32                    
        steps:
-            - uses: actions/checkout@v7
+            - uses: actions/checkout@v3

-            - uses: actions/setup-python@v7
+            - uses: actions/setup-python@v4
              with:
-                  python-version: "3.13"
-
-            - name: Install esptool
-              run: pip install "esptool>=5,<6"
+                  python-version: "3.9"

            - name: Install PlatformIO Core
              run: pip install --upgrade platformio

            - name: Build target
              run: |
-                  pio run -e ${{ matrix.target.name }}
+                  pio run -e ${{ matrix.target.name }} 

            - name: Build FS
              run: |
@@ -147,48 +118,48 @@ jobs:
                  cp .pio/build/${{ matrix.target.name }}/partitions.bin installer/firmware/
                  cp .pio/build/${{ matrix.target.name }}/spiffs.bin installer/firmware/
                  cp ~/.platformio/packages/framework-arduinoespressif32/tools/partitions/boot_app0.bin installer/firmware/
-
+              
            - name: Merge for web flashing
              run: |
                  if [ "${{ matrix.target.chip }}" == "esp32" ]; then
-                    esptool --chip esp32 merge-bin \
+                    python installer/bin/esptool/esptool.py --chip esp32 merge_bin \
                      -o installer/web_factory.bin \
-                      --flash-mode dio \
-                      --flash-freq 40m \
-                      --flash-size 4MB \
+                      --flash_mode dio \
+                      --flash_freq 40m \
+                      --flash_size 4MB \
                      0x1000 installer/firmware/bootloader.bin \
                      0x8000 installer/firmware/partitions.bin \
                      0xe000 installer/firmware/boot_app0.bin \
                      0x10000 installer/firmware/firmware.bin \
                      0x3D0000 installer/firmware/spiffs.bin
                  elif [ "${{ matrix.target.chip }}" == "esp32s2" ]; then
-                    esptool --chip esp32s2 merge-bin \
+                    python installer/bin/esptool/esptool.py --chip esp32s2 merge_bin \
                      -o installer/web_factory.bin \
-                      --flash-mode dio \
-                      --flash-freq 40m \
-                      --flash-size 4MB \
+                      --flash_mode dio \
+                      --flash_freq 40m \
+                      --flash_size 4MB \
                      0x1000 installer/firmware/bootloader.bin \
                      0x8000 installer/firmware/partitions.bin \
                      0xe000 installer/firmware/boot_app0.bin \
                      0x10000 installer/firmware/firmware.bin \
                      0x3D0000 installer/firmware/spiffs.bin
                  elif [ "${{ matrix.target.chip }}" == "esp32s3" ]; then
-                    esptool --chip esp32s3 merge-bin \
+                    python installer/bin/esptool/esptool.py --chip esp32s3 merge_bin \
                      -o installer/web_factory.bin \
-                      --flash-mode dio \
-                      --flash-freq 40m \
-                      --flash-size 8MB \
+                      --flash_mode dio \
+                      --flash_freq 40m \
+                      --flash_size 8MB \
                      0x0000 installer/firmware/bootloader.bin \
                      0x8000 installer/firmware/partitions.bin \
                      0xe000 installer/firmware/boot_app0.bin \
                      0x10000 installer/firmware/firmware.bin \
                      0x3D0000 installer/firmware/spiffs.bin
                  elif [ "${{ matrix.target.chip }}" == "esp32c3" ]; then
-                    esptool --chip esp32c3 merge-bin \
+                    python installer/bin/esptool/esptool.py --chip esp32c3 merge_bin \
                      -o installer/web_factory.bin \
-                      --flash-mode dio \
-                      --flash-freq 40m \
-                      --flash-size 4MB \
+                      --flash_mode dio \
+                      --flash_freq 40m \
+                      --flash_size 4MB \
                      0x1000 installer/firmware/bootloader.bin \
                      0x8000 installer/firmware/partitions.bin \
                      0xe000 installer/firmware/boot_app0.bin \
@@ -202,12 +173,12 @@ jobs:
            - name: Archive Files
              run: zip -r installer.zip installer/

-            - name: Rename zip for upload
-              run: mv installer.zip ${{ matrix.target.name }}.zip
-
            - name: Upload Release Asset
-              uses: softprops/action-gh-release@v3
-              with:
-                  files: ${{ matrix.target.name }}.zip
+              uses: actions/upload-release-asset@v1
              env:
                  GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+              with:
+                  upload_url: ${{ github.event.release.upload_url }}
+                  asset_path: ./installer.zip
+                  asset_name: ${{ matrix.target.name }}.zip
+                  asset_content_type: application/zip
@@ -15,11 +15,11 @@ jobs:
                - name: ttgo-lora32-v21
                  chip: esp32
        steps:
-            - uses: actions/checkout@v7
+            - uses: actions/checkout@v3

-            - uses: actions/setup-python@v7
+            - uses: actions/setup-python@v4
              with:
-                  python-version: "3.13"
+                  python-version: "3.9"

            - name: Install PlatformIO Core
              run: pip install --upgrade platformio
@@ -7,5 +7,4 @@
 /data_embed/*.gz
 installer/firmware
 installer/*.bin
-**/__pycache__/
-.claude/
+**/__pycache__/
@@ -5,7 +5,6 @@
        "platformio.platformio-ide"
    ],
    "unwantedRecommendations": [
-        "ms-vscode.cpptools-extension-pack",
-        "pioarduino.pioarduino-ide"
+        "ms-vscode.cpptools-extension-pack"
    ]
 }
@@ -2,92 +2,64 @@

 This firmware is for using ESP32 based boards with LoRa Modules and GPS to live in the APRS world.

-![Screenshot](https://github.com/richonguzman/LoRa_APRS_iGate/raw/main/images/iGateOledScreen.jpeg)
+![Screenshot](https://github.com/richonguzman/LoRa_APRS_iGate/blob/main/images/iGateOledScreen.jpeg)

 __(This iGate Firmware works with all LoRa Tracker Firmwares (specially this <a href="https://github.com/richonguzman/LoRa_APRS_Tracker" target="_blank">LoRa APRS Tracker Firmware</a>))__
 <br />

 ____________________________________________________

-# <a href="https://richonguzman.github.io/lora-igate-web-flasher/installer.html" target="_blank">WEB FLASHER/INSTALLER</a>
-
-
-# <a href="https://drive.google.com/file/d/1Hff_Szd7ks8RC7_RiV6POxPJlclbO05M/view?usp=sharing" target="_blank">LoRa APRS iGate CA2RXU Firmware Manual</a>
-
-____________________________________________________
-
-## New Web/UI
-
-| New Menu | Map |
-| --- | --- |
-| ![new menu](images/1.png) | ![map](images/2.jpg) |
-
-____________________________________________________
-
 ## You can support this project to continue to grow:

-[<img src="https://github.com/richonguzman/LoRa_APRS_Tracker/raw/main/images/github-sponsors.png">](https://github.com/sponsors/richonguzman)     [<img src="https://github.com/richonguzman/LoRa_APRS_Tracker/raw/main/images/paypalme.png">](http://paypal.me/richonguzman)
+[<img src="https://github.com/richonguzman/LoRa_APRS_Tracker/blob/main/images/github-sponsors.png">](https://github.com/sponsors/richonguzman)     [<img src="https://github.com/richonguzman/LoRa_APRS_Tracker/blob/main/images/paypalme.png">](http://paypal.me/richonguzman)
+
+<br />
+
+# WEB FLASHER/INSTALLER is <a href="https://richonguzman.github.io/lora-igate-web-flasher/installer.html" target="_blank">here</a>

 ____________________________________________________

+# WIKI

-## SUPPORTED BOARDS (<a href="https://github.com/richonguzman/LoRa_APRS_iGate/wiki/Supported-Boards-and-Buying-Links" target="_blank">Buying links</a>).
+### FAQ, BME280, TNC and more --> <a href="https://github.com/richonguzman/LoRa_APRS_iGate/wiki/00.-FAQ-(frequently-asked-questions)" target="_blank">here</a>.
+
+### Installation Guide --> <a href="https://github.com/richonguzman/LoRa_APRS_iGate/wiki/01.-Installation-Guide" target="_blank">here</a>.
+<br />
+
+# SUPPORTED BOARDS
+
+### Buying links --> <a href="https://github.com/richonguzman/LoRa_APRS_iGate/wiki/108.-Supported-Boards-and-Buying-Links" target="_blank">here</a>.

 (NOTE: all boards with 433-868-915 MHz versions)

- TTGO Lilygo LoRa32 LoRa32 V2.1 (V1.6 is the same) and T3S3 V1.2.
+- TTGO Lilygo LoRa32 T3S3 V1.2 and LoRa32 V2.1 (V1.6 is the same).

- TTGO T-Beam V1.0 , V1.1, V1.2 (also variations with SX1262 and SX1268 LoRa Modules) and Supreme V3.
+- TTGO T-Beam V1.0 , V1.1, V1.2 (also variations with SX1262 and SX1268 LoRa Modules).

 - T-Deck Plus (and also regular T-Deck with/without GPS).

- HELTEC V2, V3, V3.2, V4, T114, Wireless Stick, Wireless Stick Lite V3/V3.2, HT-CT62, Wireless Tracker, Wireless Paper.
+- HELTEC V2, V3, V3.2, T114, Wireless Stick, Wireless Stick Lite, HT-CT62, Wireless Tracker, Wireless Paper.

- RAK Wireless 4631 + 19007(or 19003), RAK3312 and RAK3112.
+- RAK Wireless 4631 + 19007(19003)

- Faketec V3 (NRF52840 + Heltec HTRA62(SX1262))
+- Faketec (NRF52840 + Heltec HTRA62(SX1262))

 - QRP Labs LightGateway 1.0 and Plus 1.0.

- ESP32 + SX1278 LoRa Module or Ebyte 400M30S (or 900M30S) or Ebyte E32 400M30S 1W LoRa Module for a DIY Versions.
+- Faketec V3 (NRF52840 + Heltec HTRA62 SX1262)
+
+- ESP32 Wroom + SX1278 LoRa Module or Ebyte 400M30S (or 900M30S) 1W LoRa Module for a DIY Versions.

 - ESP32C3 + Ebyte 400M30S(or 900M30S) 1W LoRa Module for another DIY version.

- ESP32C3 SuperMini + SX1278 (RA-01/RA-02) LoRa Module DIY version.
-
 - ESP32 + 4G/LTE A7670 Modem + SX1278 DIY Version.

 - Wemos Lolin32 Oled + SX1278 DIY Version.

- and many more...
-
 <br />

-# Timeline (Versions):
- 2026-09-30 GPS baud rate auto-detection, CAD timeout (packet dropped after 10s of busy channel)
- 2026-09-23 APRSPacketLib V1.0.7 update and many code cleaning with this.
- 2026-09-17 Real APRS Symbols added to map and TNC2 output as a posibility in TNC mode.
- 2026-08-16 New UI (Web) and also Live View over a Map to see Rx stations.
- 2026-08-10 CAD (Channel Activity Detection) and DIFS (Distributed Inter-Frame Space) added.
- 2026-03-25 More Boards, SDK update, OTA fix, GPS process update.
- 2026-02-26 9M2IBR ESP32 1W (400M30S) + GPS board added.
- 2026-02-25 Code Improvements: reduced String comparisons and improved logic for faster code execution.
- 2026-02-15 Digipeater code/logic improved.
- 2026-02-08 Heltec V2 915MHz added.
- 2026-02-05 Improved "digiBackupMode" to check "APRS-IS" server connection.
- 2026-01-07 Tactical Callsign added.
- 2026-01-05 Heltec V4 support added.
- 2025-12-22 Heltec Wireless Paper V1.2 and VisionMaster E290 Added. Thanks HA5SZI.
- 2025-12-18 TCXO and packet decoding updates.
- 2025-12-01 APRSPacketLib updates, AHT20 sensor added, INA219 support added.
- 2025-10-15 APRS Bridge for TNC added.
- 2025-10-13 Rx and Tx Frequencies are now with fully configurable.
- 2025-10-13 Startup Delay to allow the Router/Modem to start WiFiAP before connecting.
- 2025-10-12 Choose to send Beacon on Rx or Tx frequency.
- 2025-10-11 User defined NTP server and send beacon over MQTT added.
- 2025-10-10 Converted the Wiki into a PDF manual.
- 2025-09-26 Heltec Wireless Bridge support added.
- 2025-09-09 MQTT added (pub+sub), Status defined by Op now and many fixes more.
+## Timeline (Versions):
+
 - 2025-06-20 Digipeaters now with updated EcoMode (Board Sleeps until packet Rx reducing current consumption to almost 10% at idle).
 - 2025-06-20 New Boards Added: Heltec T114 MeshNode, Faketec V3 as Digipeaters and QRP Labs LightGateway Plus 1.0.
 - 2025-06-19 DateVersion format Change. Licence changed into GNU GPLv3.
@@ -109,7 +81,7 @@ ____________________________________________________
 - 2024.10.08 New EcoMode for Remote Digipeaters without WiFi/WiFiAP, Screen, Leds (Example: LILYGO LoRa32 uses only 24mA, with WifiAP 150mA). APRS Message/Queries can start/stop this mode too.
 - 2024.10.06 Cross Frequency Digipeater Rules added.
 - 2024.09.23 Libraries Update for SDK3
- 2024.09.23 Added Enconded Telemetry for Battery (+ External Voltage) in Station GPS Beacon Packet.
+- 2024.09.23 Added Enconded Telemetry for Battery (+ External Voltage) in Station GPS Beacon Packet. 
 - 2024.08.23 Wemos S2 Mini DIY LoRa added.
 - 2024.08.19 HELTEC Wireless Paper working (still missing Epaper code).
 - 2024.08.13 Web Authentication for WebUI. Thanks Mitja S57PNX.
@@ -2,45 +2,43 @@
 build_flags =
 	-Werror -Wall
 	-DELEGANTOTA_USE_ASYNC_WEBSERVER=1
-	-D RADIOLIB_EXCLUDE_CC1101=1
-	-D RADIOLIB_EXCLUDE_RF69=1
-	-D RADIOLIB_EXCLUDE_RFM2X=1
-	-D RADIOLIB_EXCLUDE_SX1231=1
-	-D RADIOLIB_EXCLUDE_SX1233=1
-	-D RADIOLIB_EXCLUDE_SI443X=1
-	-D RADIOLIB_EXCLUDE_NRF24=1
-	-D RADIOLIB_EXCLUDE_AFSK=1
-	-D RADIOLIB_EXCLUDE_APRS=1
-	-D RADIOLIB_EXCLUDE_AX25=1
-	-D RADIOLIB_EXCLUDE_BELL=1
-	-D RADIOLIB_EXCLUDE_FSK4=1
-	-D RADIOLIB_EXCLUDE_HELLSCHREIBER=1
-	-D RADIOLIB_EXCLUDE_LORAWAN=1
-	-D RADIOLIB_EXCLUDE_MORSE=1
-	-D RADIOLIB_EXCLUDE_PAGER=1
-	-D RADIOLIB_EXCLUDE_DIRECT_RECEIVE=1
-	-D RADIOLIB_EXCLUDE_RTTY=1
-	-D RADIOLIB_EXCLUDE_SSTV=1
+	-DRADIOLIB_EXCLUDE_CC1101=1
+	-DRADIOLIB_EXCLUDE_NRF24=1
+	-DRADIOLIB_EXCLUDE_RF69=1
+	-DRADIOLIB_EXCLUDE_SX1231=1
+	-DRADIOLIB_EXCLUDE_SX1233=1
+	-DRADIOLIB_EXCLUDE_SI443X=1
+	-DRADIOLIB_EXCLUDE_RFM2X=1
+	-DRADIOLIB_EXCLUDE_AFSK=1
+	-DRADIOLIB_EXCLUDE_BELL=1
+	-DRADIOLIB_EXCLUDE_HELLSCHREIBER=1
+	-DRADIOLIB_EXCLUDE_MORSE=1
+	-DRADIOLIB_EXCLUDE_RTTY=1
+	-DRADIOLIB_EXCLUDE_SSTV=1
+	-DRADIOLIB_EXCLUDE_AX25=1
+	-DRADIOLIB_EXCLUDE_DIRECT_RECEIVE=1
+	-DRADIOLIB_EXCLUDE_BELL=1
+	-DRADIOLIB_EXCLUDE_PAGER=1
+	-DRADIOLIB_EXCLUDE_FSK4=1
+	-DRADIOLIB_EXCLUDE_APRS=1
+	-DRADIOLIB_EXCLUDE_LORAWAN=1
 	-I variants/${PIOENV}
 lib_deps =
-	adafruit/Adafruit Unified Sensor @ 1.1.15
-	adafruit/Adafruit AHTX0 @ 2.0.6
-	adafruit/Adafruit BME280 Library @ 2.3.0
-	adafruit/Adafruit BMP280 Library @ 3.0.0
-	adafruit/Adafruit BME680 Library @ 2.0.6
-	adafruit/Adafruit INA219 @ 1.2.3
+	adafruit/Adafruit Unified Sensor @ 1.1.14
+	adafruit/Adafruit BME280 Library @ 2.2.4
+	adafruit/Adafruit BMP280 Library @ 2.6.8
+	adafruit/Adafruit BME680 Library @ 2.0.4
 	adafruit/Adafruit Si7021 Library @ 1.5.3
-	ayushsharma82/ElegantOTA @ 3.1.7
-	bblanchon/ArduinoJson @ 7.4.3
-	jgromes/RadioLib @ 7.6.0
-	knolleary/PubSubClient @ 2.8
-	ESP32Async/AsyncTCP @ 3.5.0
-	ESP32Async/ESPAsyncWebServer @ 3.12.1
-	mikalhart/TinyGPSPlus @ 1.1.0
-	richonguzman/APRSPacketLib @ 1.0.10
+	arduino-libraries/NTPClient @ 3.2.1
+	ayushsharma82/ElegantOTA @ 3.1.5
+	bblanchon/ArduinoJson @ 6.21.3
+	jgromes/RadioLib @ 7.1.0
+	mathieucarbou/AsyncTCP @ 3.2.5
+	mathieucarbou/ESPAsyncWebServer @ 3.2.3
+	mikalhart/TinyGPSPlus @ 1.0.3	
 display_libs =
-	adafruit/Adafruit GFX Library @ 1.12.6
-	adafruit/Adafruit SSD1306 @ 2.5.17
+	adafruit/Adafruit GFX Library @ 1.11.9
+	adafruit/Adafruit SSD1306 @ 2.5.10
 usb_flags=
 	-DARDUINO_USB_MODE=1
-	-DARDUINO_USB_CDC_ON_BOOT=1
+	-DARDUINO_USB_CDC_ON_BOOT=1 
@@ -17,41 +17,31 @@
        "path": "WIDE1-1",
        "sendViaAPRSIS": false,
        "sendViaRF": false,
-        "beaconFreq": 1,
        "statusActive": false,
-        "statusPacket": "",
-        "gpsActive": false,
-        "ambiguityLevel": 0
+        "statusPacket": ""
    },
    "aprs_is": {
        "active": false,
-        "messagesToRF": false,
-        "objectsToRF": false,
-        "server": "rotate.aprs2.net",
        "passcode": "XYZVW",
+        "server": "rotate.aprs2.net",
        "port": 14580,
-        "filter": "m/10"
+        "filter": "m/10",
+        "messagesToRF": false,
+        "objectsToRF": false
    },
-    "personalNote": "",
-    "blacklist": "",
    "digi": {
        "mode": 0,
-        "ecoMode": 0,
-        "backupDigiMode": false
+        "ecoMode": 0
    },
    "lora": {
-        "rxActive": true,
-        "rxFreq": 433775000,
-        "rxSpreadingFactor": 12,
-        "rxCodingRate4": 5,
-        "rxSignalBandwidth": 125000,
-        "txActive": false,
        "txFreq": 433775000,
-        "txSpreadingFactor": 12,
-        "txCodingRate4": 5,
-        "txSignalBandwidth": 125000,
+        "rxFreq": 433775000,
+        "spreadingFactor": 12,
+        "signalBandwidth": 125000,
+        "codingRate4": 5,
        "power": 20,
-        "cadActive": true
+        "txActive": false,
+        "rxActive": true
    },
    "display": {
        "alwaysOn": true,
@@ -63,12 +53,11 @@
        "monitorInternalVoltage": false,
        "internalSleepVoltage": 2.9,
        "sendExternalVoltage": false,
+        "externalVoltagePin": 34,
        "monitorExternalVoltage": false,
        "externalSleepVoltage": 10.9,
-        "useExternalI2CSensor": false,
        "voltageDividerR1": 100.0,
        "voltageDividerR2": 27.0,
-        "externalVoltagePin": 34,
        "sendVoltageAsTelemetry": false
 	},
    "wxsensor": {
@@ -85,17 +74,7 @@
    "tnc": {
        "enableServer": false,
        "enableSerial": false,
-        "acceptOwn": false,
-        "aprsBrigdeActive": false
-    },
-    "mqtt": {
-        "active": false,
-        "server": "",
-        "topic": "",
-        "username": "",
-        "password": "",
-        "port": 1883,
-        "beaconOverMqtt": false
+        "acceptOwn": false
    },
    "ota": {
        "username": "",
@@ -105,18 +84,19 @@
        "username": "admin",
        "password": ""
    },
+    "ntp": {
+        "gmtCorrection": 0.0
+    },
    "remoteManagement": {
        "managers": "",
        "rfOnly": true
-    },
-    "ntp": {
-        "server": "pool.ntp.org",
-        "gmtCorrection": 0.0
-    },
+    },        
    "other": {
        "rememberStationTime": 30,
+        "backupDigiMode": false,
        "rebootMode": false,
-        "rebootModeTime": 6,
-        "startupDelay": 0
-    }
+        "rebootModeTime": 6
+    },
+    "personalNote": "",
+    "blacklist": ""
 }
@@ -1,661 +0,0 @@
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-.leaflet-pane,
-.leaflet-tile,
-.leaflet-marker-icon,
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-.leaflet-layer {
-	position: absolute;
-	left: 0;
-	top: 0;
-	}
-.leaflet-container {
-	overflow: hidden;
-	}
-.leaflet-tile,
-.leaflet-marker-icon,
-.leaflet-marker-shadow {
-	-webkit-user-select: none;
-	   -moz-user-select: none;
-	        user-select: none;
-	  -webkit-user-drag: none;
-	}
-/* Prevents IE11 from highlighting tiles in blue */
-.leaflet-tile::selection {
-	background: transparent;
-}
-/* Safari renders non-retina tile on retina better with this, but Chrome is worse */
-.leaflet-safari .leaflet-tile {
-	image-rendering: -webkit-optimize-contrast;
-	}
-/* hack that prevents hw layers "stretching" when loading new tiles */
-.leaflet-safari .leaflet-tile-container {
-	width: 1600px;
-	height: 1600px;
-	-webkit-transform-origin: 0 0;
-	}
-.leaflet-marker-icon,
-.leaflet-marker-shadow {
-	display: block;
-	}
-/* .leaflet-container svg: reset svg max-width decleration shipped in Joomla! (joomla.org) 3.x */
-/* .leaflet-container img: map is broken in FF if you have max-width: 100% on tiles */
-.leaflet-container .leaflet-overlay-pane svg {
-	max-width: none !important;
-	max-height: none !important;
-	}
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-.leaflet-container .leaflet-shadow-pane img,
-.leaflet-container .leaflet-tile-pane img,
-.leaflet-container img.leaflet-image-layer,
-.leaflet-container .leaflet-tile {
-	max-width: none !important;
-	max-height: none !important;
-	width: auto;
-	padding: 0;
-	}
-
-.leaflet-container img.leaflet-tile {
-	/* See: https://bugs.chromium.org/p/chromium/issues/detail?id=600120 */
-	mix-blend-mode: plus-lighter;
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-
-.leaflet-container.leaflet-touch-zoom {
-	-ms-touch-action: pan-x pan-y;
-	touch-action: pan-x pan-y;
-	}
-.leaflet-container.leaflet-touch-drag {
-	-ms-touch-action: pinch-zoom;
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-	touch-action: pinch-zoom;
-}
-.leaflet-container.leaflet-touch-drag.leaflet-touch-zoom {
-	-ms-touch-action: none;
-	touch-action: none;
-}
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-}
-.leaflet-container a {
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-}
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-.leaflet-overlay-pane svg {
-	-moz-user-select: none;
-	}
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-.leaflet-pane         { z-index: 400; }
-
-.leaflet-tile-pane    { z-index: 200; }
-.leaflet-overlay-pane { z-index: 400; }
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-.leaflet-marker-pane  { z-index: 600; }
-.leaflet-tooltip-pane   { z-index: 650; }
-.leaflet-popup-pane   { z-index: 700; }
-
-.leaflet-map-pane canvas { z-index: 100; }
-.leaflet-map-pane svg    { z-index: 200; }
-
-.leaflet-vml-shape {
-	width: 1px;
-	height: 1px;
-	}
-.lvml {
-	behavior: url(#default#VML);
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-/* control positioning */
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-.leaflet-control {
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-.leaflet-top {
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-.leaflet-bottom {
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-	}
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-	}
-.leaflet-control {
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-.leaflet-right .leaflet-control {
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-.leaflet-top .leaflet-control {
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-	}
-.leaflet-bottom .leaflet-control {
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-.leaflet-right .leaflet-control {
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-.leaflet-fade-anim .leaflet-popup {
-	opacity: 0;
-	-webkit-transition: opacity 0.2s linear;
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-.leaflet-fade-anim .leaflet-map-pane .leaflet-popup {
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-.leaflet-zoom-animated {
-	-webkit-transform-origin: 0 0;
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-svg.leaflet-zoom-animated {
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-.leaflet-zoom-anim .leaflet-zoom-animated {
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-.leaflet-zoom-anim .leaflet-tile,
-.leaflet-pan-anim .leaflet-tile {
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-	   -moz-transition: none;
-	        transition: none;
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-.leaflet-zoom-anim .leaflet-zoom-hide {
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-/* cursors */
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-.leaflet-interactive {
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-	}
-.leaflet-grab {
-	cursor: -webkit-grab;
-	cursor:    -moz-grab;
-	cursor:         grab;
-	}
-.leaflet-crosshair,
-.leaflet-crosshair .leaflet-interactive {
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-	}
-.leaflet-popup-pane,
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-	cursor: auto;
-	}
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-.leaflet-dragging .leaflet-grab .leaflet-interactive,
-.leaflet-dragging .leaflet-marker-draggable {
-	cursor: move;
-	cursor: -webkit-grabbing;
-	cursor:    -moz-grabbing;
-	cursor:         grabbing;
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-/* marker & overlays interactivity */
-.leaflet-marker-icon,
-.leaflet-marker-shadow,
-.leaflet-image-layer,
-.leaflet-pane > svg path,
-.leaflet-tile-container {
-	pointer-events: none;
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-.leaflet-marker-icon.leaflet-interactive,
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-.leaflet-pane > svg path.leaflet-interactive,
-svg.leaflet-image-layer.leaflet-interactive path {
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-	pointer-events: auto;
-	}
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-/* visual tweaks */
-
-.leaflet-container {
-	background: #ddd;
-	outline-offset: 1px;
-	}
-.leaflet-container a {
-	color: #0078A8;
-	}
-.leaflet-zoom-box {
-	border: 2px dotted #38f;
-	background: rgba(255,255,255,0.5);
-	}
-
-
-/* general typography */
-.leaflet-container {
-	font-family: "Helvetica Neue", Arial, Helvetica, sans-serif;
-	font-size: 12px;
-	font-size: 0.75rem;
-	line-height: 1.5;
-	}
-
-
-/* general toolbar styles */
-
-.leaflet-bar {
-	box-shadow: 0 1px 5px rgba(0,0,0,0.65);
-	border-radius: 4px;
-	}
-.leaflet-bar a {
-	background-color: #fff;
-	border-bottom: 1px solid #ccc;
-	width: 26px;
-	height: 26px;
-	line-height: 26px;
-	display: block;
-	text-align: center;
-	text-decoration: none;
-	color: black;
-	}
-.leaflet-bar a,
-.leaflet-control-layers-toggle {
-	background-position: 50% 50%;
-	background-repeat: no-repeat;
-	display: block;
-	}
-.leaflet-bar a:hover,
-.leaflet-bar a:focus {
-	background-color: #f4f4f4;
-	}
-.leaflet-bar a:first-child {
-	border-top-left-radius: 4px;
-	border-top-right-radius: 4px;
-	}
-.leaflet-bar a:last-child {
-	border-bottom-left-radius: 4px;
-	border-bottom-right-radius: 4px;
-	border-bottom: none;
-	}
-.leaflet-bar a.leaflet-disabled {
-	cursor: default;
-	background-color: #f4f4f4;
-	color: #bbb;
-	}
-
-.leaflet-touch .leaflet-bar a {
-	width: 30px;
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-	}
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-	border-bottom-left-radius: 2px;
-	border-bottom-right-radius: 2px;
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-/* zoom control */
-
-.leaflet-control-zoom-in,
-.leaflet-control-zoom-out {
-	font: bold 18px 'Lucida Console', Monaco, monospace;
-	text-indent: 1px;
-	}
-
-.leaflet-touch .leaflet-control-zoom-in, .leaflet-touch .leaflet-control-zoom-out  {
-	font-size: 22px;
-	}
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-
-/* layers control */
-
-.leaflet-control-layers {
-	box-shadow: 0 1px 5px rgba(0,0,0,0.4);
-	background: #fff;
-	border-radius: 5px;
-	}
-.leaflet-control-layers-toggle {
-	background-image: url(images/layers.png);
-	width: 36px;
-	height: 36px;
-	}
-.leaflet-retina .leaflet-control-layers-toggle {
-	background-image: url(images/layers-2x.png);
-	background-size: 26px 26px;
-	}
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-	width: 44px;
-	height: 44px;
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-.leaflet-control-layers .leaflet-control-layers-list,
-.leaflet-control-layers-expanded .leaflet-control-layers-toggle {
-	display: none;
-	}
-.leaflet-control-layers-expanded .leaflet-control-layers-list {
-	display: block;
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-.leaflet-control-layers-expanded {
-	padding: 6px 10px 6px 6px;
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-.leaflet-control-layers-scrollbar {
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-	}
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-	margin-top: 2px;
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-	}
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-	height: 0;
-	border-top: 1px solid #ddd;
-	margin: 5px -10px 5px -6px;
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-/* Default icon URLs */
-.leaflet-default-icon-path { /* used only in path-guessing heuristic, see L.Icon.Default */
-	background-image: url(images/marker-icon.png);
-	}
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-
-/* attribution and scale controls */
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-.leaflet-container .leaflet-control-attribution {
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-.leaflet-control-scale-line {
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-	text-decoration: underline;
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-	vertical-align: baseline !important;
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-	height: 0.6669em;
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-.leaflet-touch .leaflet-control-attribution,
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-	background-clip: padding-box;
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-/* popup */
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-.leaflet-popup {
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-	text-align: center;
-	margin-bottom: 20px;
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-/* Directions */
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@@ -1,6 +0,0 @@
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- */
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e?console.warn("wrong listener type: "+typeof e):!1!==(e=this._listens(Line truncated
-//# sourceMappingURL=leaflet.js.map
@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -27,18 +27,24 @@ namespace APRS_IS_Utils {
    void    upload(const String& line);
    void    connect();

-    void    updateWiFiAPRSISDisplayInfo();
+    void    checkStatus();
+    String  checkForStartingBytes(const String& packet);

    String  buildPacketToUpload(const String& packet);
-    bool    processReceivedLoRaMessage(const String& sender, const String& packet);
+    bool    processReceivedLoRaMessage(const String& sender, const String& packet, bool thirdParty);
    void    processLoRaPacket(const String& packet);

    String  buildPacketToTx(const String& aprsisPacket, uint8_t packetType);
-    void    processAPRSISPacket(const String& packet);
+    void    processAPRSISPacket();//const String& packet);
    void    listenAPRSIS();

    void    firstConnection();

+    bool    startListenerAPRSISTask(uint32_t stackSize = 8192, UBaseType_t priority = 1);
+    void    stopListenerAPRSISTask();
+    void    suspendListenerAPRSISTask();
+    void    resumeListenerAPRSISTask();
+
 }

 #endif
@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -32,6 +32,9 @@ namespace BATTERY_Utils {
    float   checkExternalVoltage();
    void    startupBatteryHealth();

+    String  generateEncodedTelemetryBytes(float value, bool firstBytes, byte voltageType);
+    String  generateEncodedTelemetry();
+
 }

 #endif
@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -32,7 +32,6 @@ public:

 class WiFi_Auto_AP {
 public:
-    bool    enabled;            // Enable Auto AP
    String  password;
    int     timeout;
 };
@@ -42,18 +41,16 @@ public:
    double  latitude;
    double  longitude;
    String  comment;
-    int     rfCommentEveryXBeacons;
    int     interval;
    String  overlay;
    String  symbol;
-    String  path;
-    bool    sendViaAPRSIS;
+    String  path;    
    bool    sendViaRF;
-    int     beaconFreq;
+    bool    sendViaAPRSIS;
+    bool    gpsActive;
+    bool    gpsAmbiguity;
    bool    statusActive;
    String  statusPacket;
-    bool    gpsActive;
-    int     ambiguityLevel;
 };

 class APRS_IS {
@@ -71,23 +68,18 @@ class DIGI {
 public:
    int     mode;
    int     ecoMode;        // 0 = Not Active | 1 = Ultra EcoMode | 2 = Not Active (WiFi OFF, Serial ON)
-    bool    backupDigiMode;
 };

 class LoraModule {
 public:
-    bool    rxActive;
-    long    rxFreq;
-    int     rxSpreadingFactor;
-    int     rxCodingRate4;
-    long    rxSignalBandwidth;
-    bool    txActive;
    long    txFreq;
-    int     txSpreadingFactor;
-    int     txCodingRate4;
-    long    txSignalBandwidth;
+    long    rxFreq;
+    bool    txActive;
+    bool    rxActive;
+    int     spreadingFactor;
+    long    signalBandwidth;
+    int     codingRate4;
    int     power;
-    bool    cadActive;
 };

 class Display {
@@ -106,7 +98,6 @@ public:
    int     externalVoltagePin;
    bool    monitorExternalVoltage;
    float   externalSleepVoltage;
-    bool    useExternalI2CSensor;
    float   voltageDividerR1;
    float   voltageDividerR2;
    bool    sendVoltageAsTelemetry;
@@ -132,8 +123,6 @@ public:
    bool    enableServer;
    bool    enableSerial;
    bool    acceptOwn;
-    bool    aprsBridgeActive;
-    bool    kissProtocol;    // true = KISS, false = TNC2 -- applies to both Serial and TCP server
 };

 class OTA {
@@ -151,7 +140,6 @@ public:

 class NTP {
 public:
-    String  server;
    float   gmtCorrection;
 };

@@ -161,25 +149,13 @@ public:
    bool    rfOnly;
 };

-class MQTT {
-public:
-    bool    active;
-    String  server;
-    String  topic;
-    String  username;
-    String  password;
-    int     port;
-    bool    beaconOverMqtt;
-};
-
 class Configuration {
 public:
    String                  callsign;
-    String                  tacticalCallsign;
    int                     rememberStationTime;
+    bool                    backupDigiMode;
    bool                    rebootMode;
    int                     rebootModeTime;
-    int                     startupDelay;
    String                  personalNote;
    String                  blacklist;
    std::vector<WiFi_AP>    wifiAPs;
@@ -192,20 +168,19 @@ public:
    BATTERY                 battery;
    WXSENSOR                wxsensor;
    SYSLOG                  syslog;
-    TNC                     tnc;
+    TNC                     tnc;  
    OTA                     ota;
    WEBADMIN                webadmin;
-    NTP                     ntp;
+    NTP                     ntp;    
    REMOTE_MANAGEMENT       remoteManagement;
-    MQTT                    mqtt;

-    void setup();
-    void setDefaultValues();
-    bool writeFile();
+    void init();
+    void writeFile();
+    Configuration();

 private:
    bool readFile();
    String _filePath;
 };

-#endif
+#endif
@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -24,9 +24,10 @@

 namespace DIGI_Utils {

-    String  buildPacket(const String& path, const String& packet, bool crossFreq);
-    String  generateDigipeatedPacket(const String& packet);
+    String  buildPacket(const String& path, const String& packet, bool thirdParty, bool crossFreq);
+    String  generateDigipeatedPacket(const String& packet, bool thirdParty);
    void    processLoRaPacket(const String& packet);
+    void    checkEcoMode();

 }

@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -21,7 +21,6 @@

 #include <Arduino.h>

-
 #define SCREEN_ADDRESS  0x3C    ///< See datasheet for Address; 0x3D for 128x64, 0x3C for 128x32

 void displaySetup();
@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -23,9 +23,15 @@


 namespace GPS_Utils {
-
+    
+    String  getiGateLoRaBeaconPacket();
+    char    *ax25_base91enc(char *s, uint8_t n, uint32_t v);
+    String  encodeGPS(float latitude, float longitude, const String& overlay, const String& symbol);
+    void    generateBeaconFirstPart();
    void    generateBeacons();
-    String  buildDistanceAndComment(float latitude, float longitude, const String& comment);
+    String  decodeEncodedGPS(const String& packet);
+    String  getReceivedGPS(const String& packet);
+    String  getDistanceAndComment(const String& packet);

    void    setup();
    void    getData();
@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -24,7 +24,6 @@

 namespace LoRa_Utils {

-    int     validPower(int requested);
    void    setup();
    void    sendNewPacket(const String& newPacket);
    String  receivePacketFromSleep();
@@ -1,47 +0,0 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
- * This file is part of LoRa APRS iGate.
- *
- * LoRa APRS iGate is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * LoRa APRS iGate is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
- */
-
-#ifndef MAP_UTILS_H_
-#define MAP_UTILS_H_
-
-#include <Arduino.h>
-#include <vector>
-
-
-struct MapStation {
-    char     callsign[10];      // "XX9XXX-NN" + null  -> clave para deduplicar
-    float    latitude;          // grados decimales (+N / -S)
-    float    longitude;         // grados decimales (+E / -W)
-    char     symbol[3];         // tabla + codigo APRS (ej "/>"), "" si no hay
-    int16_t  rssi;              // ultimo RSSI
-    float    snr;               // ultimo SNR
-    uint16_t count;             // nro de paquetes oidos de esa estacion
-    char     lastHeard[10];     // "HH:MM:SS" si hay NTP valido, "" si no
-    char     path[96];          // last path received
-    uint32_t lastHeardMillis;   // millis() -> ordenar / expirar (no se muestra)
-    bool     heardDirect;       // true si ALGUNA VEZ se oyo sin digipeaters (no se resetea)
-};
-
-namespace MAP_Utils {
-
-    void    upsert(const String& callsign, float latitude, float longitude, const String& path, const String& symbol, int rssi, float snr);
-    String  getStationsJson();
-
-}
-
-#endif
@@ -1,34 +0,0 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
- * This file is part of LoRa APRS iGate.
- *
- * LoRa APRS iGate is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * LoRa APRS iGate is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
- */
-
-#ifndef MQTT_UTILS_H_
-#define MQTT_UTILS_H_
-
-#include <Arduino.h>
-
-
-namespace MQTT_Utils {
-
-    void sendToMqtt(const String& packet);
-    void connect();
-    void loop();
-    void setup();
-
-}
-
- #endif
@@ -1,106 +0,0 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
- * This file is part of LoRa APRS iGate.
- *
- * LoRa APRS iGate is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * LoRa APRS iGate is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
- */
-
-#include <Arduino.h>
-#include <SPI.h>
-#include <WiFi.h>
-#include <ETH.h>
-#include <vector>
-
-/**
- * Class for managing network connections
- */
-class NetworkManager
-{
-private:
-    class WiFiNetwork {
-    public:
-        String ssid;
-        String psk;
-    };
-
-    bool _wifiAPmode = false;
-    bool _wifiSTAmode = false;
-    bool _ethernetMode = false;
-    bool _ethernetConnected = false;
-    unsigned long _apStartup = 0;
-    unsigned long _apTimeout = 0;
-
-    String _hostName = "";
-    std::vector<WiFiNetwork> _wifiNetworks;
-    volatile uint8_t _lastWiFiDisconnectReason = 0;
-    String _wifiAuthFailSSID = "";
-
-    int _findWiFiNetworkIndex(const String& ssid) const;
-    bool _connectWiFi(const WiFiNetwork& network);
-    bool _isWiFiAuthFailure() const;
-    void _processAPTimeout();
-    void _onNetworkEvent(arduino_event_id_t event, arduino_event_info_t /*info*/);
-
-public:
-    // Constructor
-    NetworkManager();
-
-    // Destructor
-    ~NetworkManager();
-
-    // Initialize network module
-    bool setup();
-    void loop();
-
-    void setHostName(const String& hostName);
-
-    // WiFi methods
-    bool setupAP(String apName, String apPsk = "");
-    bool disableAP();
-    void setAPTimeout(unsigned long timeout);
-    void addWiFiNetwork(const String& ssid, const String& psk = "");
-    void clearWiFiNetworks();
-    bool hasWiFiNetworks() const;
-    size_t getWiFiNetworkCount() const;
-    bool connectWiFi();
-    bool connectWiFi(const String& ssid, const String& psk = "");
-    bool disconnectWiFi();
-    String getWiFiSSID() const;
-    String getWiFiAPSSID() const;
-    String getWiFiAuthFailSSID() const;
-    IPAddress getWiFiIP() const;
-    IPAddress getWiFiAPIP() const;
-    wifi_mode_t getWiFiMode() const;
-    uint8_t* getWiFimacAddress(uint8_t* mac);
-    String getWiFimacAddress(void) const;
-
-    // Ethernet methods
-    bool ethernetConnect(eth_phy_type_t type, uint8_t phy_addr, uint8_t mdc, uint8_t mdio, int power, eth_clock_mode_t clock_mode, bool use_mac_from_efuse = false);
-    bool setEthernetIP(const String& staticIP, const String& gateway, const String& subnet, const String& dns1, const String& dns2);
-    IPAddress getEthernetIP() const;
-    String getEthernetMACAddress() const;
-
-    // Check if any network is available
-    bool isConnected() const;
-
-    // Check if specific network is connected
-    bool isWiFiConnected() const;
-    bool isEthernetConnected() const;
-    bool isModemConnected() const;
-
-    bool isWifiAPActive() const;
-
-    // Check if any network interface was started (lwip TCP/IP stack is initialized)
-    bool hasActiveInterface() const;
-};
@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -24,10 +24,9 @@

 namespace NTP_Utils {

-    bool    setup();
+    void    setup();
    void    update();
    String  getFormatedTime();
-    String  getFormatedDate();

 }

@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -29,26 +29,24 @@

 namespace POWER_Utils {

-    #ifdef VEXT_CTRL_PIN
+    #ifdef VEXT_CTRL
        void vext_ctrl_ON();
        void vext_ctrl_OFF();
    #endif

-    #ifdef ADC_CTRL_PIN
+    #ifdef ADC_CTRL
        void adc_ctrl_ON();
        void adc_ctrl_OFF();
    #endif

    double  getBatteryVoltage();
    bool    isBatteryConnected();
+    void    activateMeasurement();
    void    activateGPS();
    void    deactivateGPS();
    void    activateLoRa();
    void    deactivateLoRa();
    bool    begin(TwoWire &port);
-    #ifdef SOLAR_CHARGE_PIN
-        void checkSolarCharge();
-    #endif
    void    setup();

 }
@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -24,8 +24,7 @@

 namespace QUERY_Utils {

-    bool    isQuery(const String& message);
-    String  process(const String& query, const String& station, bool queryFromAPRSIS, bool thirdParty);
+    String process(const String& query, const String& station, bool queryFromAPRSIS, bool thirdParty);

 }

@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -21,9 +21,8 @@

 #include <Arduino.h>

-
 namespace SLEEP_Utils {
-
+    
    void setup();
    void checkWakeUpFlag();
    void startSleeping();
@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -23,6 +23,12 @@
 #include <Arduino.h>


+struct Packet25SegBuffer {
+    uint32_t    receivedTime;
+    String      station;
+    String      payload;
+};
+
 struct LastHeardStation {
    uint32_t    lastHeardTime;
    String      station;
@@ -37,10 +43,11 @@ namespace STATION_Utils {
    void deleteNotHeard();
    void updateLastHeard(const String& station);
    bool wasHeard(const String& station);
-    bool isIn25SegHashBuffer(const String& station, const String& textMessage);
+    void clean25SegBuffer();
+    bool check25SegBuffer(const String& station, const String& textMessage);
    void processOutputPacketBufferUltraEcoMode();
    void processOutputPacketBuffer();
-    void addToOutputPacketBuffer(const String& packet, bool flag = false);
+    void addToOutputPacketBuffer(const String& packet);

 }

@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -19,16 +19,12 @@
 #ifndef SYSLOG_H_
 #define SYSLOG_H_

-#include <APRSPacketLib.h>
 #include <Arduino.h>


 namespace SYSLOG_Utils {

-    void logLoRaRx(APRSPacket& aprsPacket, const String& packet, const int rssi, const float snr, const int freqError);
-    void logAPRSISTx(const String& packet);
-    void logLoRaTx(const String& packet);
-    void logCRCError(const String& packet, const int rssi, const float snr, const int freqError);
+    void log(const uint8_t type ,const String& packet, const int rssi, const float snr, const int freqError);
    void setup();

 }
@@ -1,34 +0,0 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
- * This file is part of LoRa APRS iGate.
- *
- * LoRa APRS iGate is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * LoRa APRS iGate is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
- */
-
-#ifndef TELEMETRY_UTILS_H_
-#define TELEMETRY_UTILS_H_
-
-#include <Arduino.h>
-
-
-namespace TELEMETRY_Utils {
-
-    void    sendEquationsUnitsParameters();
-    String  generateEncodedTelemetryBytes(float value, bool counterBytes, byte telemetryType);
-    String  generateEncodedTelemetry();
-    void    checkEUPInterval();
-
-}
-
-#endif
@@ -1,41 +0,0 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
- * This file is part of LoRa APRS iGate.
- *
- * LoRa APRS iGate is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * LoRa APRS iGate is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
- */
-
-// Fan / thermal control adapted from KJ7NYE's LoRa_FieldOps_APRS_Tracker (GPLv3)
-
-#ifndef THERMAL_UTILS_H_
-#define THERMAL_UTILS_H_
-
-#include "board_pinout.h"
-
-#ifdef FAN_CTRL_PIN
-
-namespace THERMAL_Utils {
-
-    void    setup();
-    void    monitor();
-    void    onTxStart();
-    void    onTxEnd();
-    void    turnOffFan();
-    bool    isTxBlocked();
-
-}
-
-#endif
-
-#endif
@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -27,8 +27,8 @@ namespace TNC_Utils {
    void setup();
    void loop();

-    void sendToClients(const String& packet, bool stripBytes = false);
-    void sendToSerial(const String& packet, bool stripBytes = false);
+    void sendToClients(const String& packet);
+    void sendToSerial(const String& packet);

 }

@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -19,12 +19,11 @@
 #ifndef UTILS_H_
 #define UTILS_H_

-#include <APRSPacketLib.h>
 #include <Arduino.h>

+
 class ReceivedPacket {
 public:
-    String  rxDate;
    String  rxTime;
    String  packet;
    int     RSSI;
@@ -36,20 +35,17 @@ namespace Utils {
    void    processStatus();
    String  getLocalIP();
    void    setupDisplay();
-    void    showActiveStations();
+    void    activeStations();
    void    checkBeaconInterval();
    void    checkDisplayInterval();
    void    validateFreqs();
-    String  padForDisplay(const String& text);
-    void    updateLoRaPacketDisplayInfo(APRSPacket& aprsPacket, const uint8_t packetType);
-    void    updateAPRSISPacketDisplayInfo(const String& packet);
+    void    typeOfPacket(const String& packet, const uint8_t packetType);
    void    print(const String& text);
    void    println(const String& text);
    void    checkRebootMode();
    void    checkRebootTime();
    void    checkSleepByLowBatteryVoltage(uint8_t mode);
-    bool    callsignIsValid(const String& callsign);
-    void    startupDelay();
+    bool    checkValidCallsign(const String& callsign);

 }

@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -27,6 +27,7 @@ namespace WIFI_Utils {
    void checkWiFi();
    void startAutoAP();
    void startWiFi();
+    void checkAutoAPTimeout();
    void setup();

 }
@@ -1,17 +1,17 @@
-/* Copyright (C) 2026 Ricardo Guzman - CA2RXU
- *
+/* Copyright (C) 2025 Ricardo Guzman - CA2RXU
+ * 
 * This file is part of LoRa APRS iGate.
- *
+ * 
 * LoRa APRS iGate is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or 
 * (at your option) any later version.
- *
+ * 
 * LoRa APRS iGate is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
- *
+ * 
 * You should have received a copy of the GNU General Public License
 * along with LoRa APRS iGate. If not, see <https://www.gnu.org/licenses/>.
 */
@@ -20,7 +20,6 @@
 #define WX_UTILS_H_

 #include <Adafruit_Sensor.h>
-#include <Adafruit_AHTX0.h>
 #include <Adafruit_BME280.h>
 #include <Adafruit_BMP280.h>
 #include <Adafruit_BME680.h>
@@ -36,7 +35,6 @@ namespace WX_Utils {
    String  generateHumString(const float sensorHum);
    String  generatePresString(const float sensorPres);
    String  readDataSensor();
-    float   readBoardTemperature();

 }

@@ -0,0 +1,34 @@
+#!/usr/bin/env python
+#
+# SPDX-FileCopyrightText: 2014-2022 Fredrik Ahlberg, Angus Gratton,
+# Espressif Systems (Shanghai) CO LTD, other contributors as noted.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This executable script is a thin wrapper around the main functionality
+# in the esptool Python package
+
+# When updating this script, please also update espefuse.py and espsecure.py
+
+import contextlib
+import os
+import sys
+
+if os.name != "nt":
+    # Linux/macOS: remove current script directory to avoid importing this file
+    # as a module; we want to import the installed esptool module instead
+    with contextlib.suppress(ValueError):
+        if sys.path[0].endswith("/bin"):
+            sys.path.pop(0)
+        sys.path.remove(os.path.dirname(sys.executable))
+
+    # Linux/macOS: delete imported module entry to force Python to load
+    # the module from scratch; this enables importing esptool module in
+    # other Python scripts
+    with contextlib.suppress(KeyError):
+        del sys.modules["esptool"]
+
+import esptool
+
+if __name__ == "__main__":
+    esptool._main()
@@ -0,0 +1,9 @@
+# SPDX-FileCopyrightText: 2014-2022 Fredrik Ahlberg, Angus Gratton,
+# Espressif Systems (Shanghai) CO LTD, other contributors as noted.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import esptool
+
+if __name__ == "__main__":
+    esptool._main()
@@ -0,0 +1,92 @@
+# SPDX-FileCopyrightText: 2014-2023 Espressif Systems (Shanghai) CO LTD,
+# other contributors as noted.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import configparser
+import os
+
+CONFIG_OPTIONS = [
+    "timeout",
+    "chip_erase_timeout",
+    "max_timeout",
+    "sync_timeout",
+    "md5_timeout_per_mb",
+    "erase_region_timeout_per_mb",
+    "erase_write_timeout_per_mb",
+    "mem_end_rom_timeout",
+    "serial_write_timeout",
+    "connect_attempts",
+    "write_block_attempts",
+    "reset_delay",
+    "custom_reset_sequence",
+]
+
+
+def _validate_config_file(file_path, verbose=False):
+    if not os.path.exists(file_path):
+        return False
+
+    cfg = configparser.RawConfigParser()
+    try:
+        cfg.read(file_path, encoding="UTF-8")
+        # Only consider it a valid config file if it contains [esptool] section
+        if cfg.has_section("esptool"):
+            if verbose:
+                unknown_opts = list(set(cfg.options("esptool")) - set(CONFIG_OPTIONS))
+                unknown_opts.sort()
+                no_of_unknown_opts = len(unknown_opts)
+                if no_of_unknown_opts > 0:
+                    suffix = "s" if no_of_unknown_opts > 1 else ""
+                    print(
+                        "Ignoring unknown config file option{}: {}".format(
+                            suffix, ", ".join(unknown_opts)
+                        )
+                    )
+            return True
+    except (UnicodeDecodeError, configparser.Error) as e:
+        if verbose:
+            print(f"Ignoring invalid config file {file_path}: {e}")
+    return False
+
+
+def _find_config_file(dir_path, verbose=False):
+    for candidate in ("esptool.cfg", "setup.cfg", "tox.ini"):
+        cfg_path = os.path.join(dir_path, candidate)
+        if _validate_config_file(cfg_path, verbose):
+            return cfg_path
+    return None
+
+
+def load_config_file(verbose=False):
+    set_with_env_var = False
+    env_var_path = os.environ.get("ESPTOOL_CFGFILE")
+    if env_var_path is not None and _validate_config_file(env_var_path):
+        cfg_file_path = env_var_path
+        set_with_env_var = True
+    else:
+        home_dir = os.path.expanduser("~")
+        os_config_dir = (
+            f"{home_dir}/.config/esptool"
+            if os.name == "posix"
+            else f"{home_dir}/AppData/Local/esptool/"
+        )
+        # Search priority: 1) current dir, 2) OS specific config dir, 3) home dir
+        for dir_path in (os.getcwd(), os_config_dir, home_dir):
+            cfg_file_path = _find_config_file(dir_path, verbose)
+            if cfg_file_path:
+                break
+
+    cfg = configparser.ConfigParser()
+    cfg["esptool"] = {}  # Create an empty esptool config for when no file is found
+
+    if cfg_file_path is not None:
+        # If config file is found and validated, read and parse it
+        cfg.read(cfg_file_path)
+        if verbose:
+            msg = " (set with ESPTOOL_CFGFILE)" if set_with_env_var else ""
+            print(
+                f"Loaded custom configuration from "
+                f"{os.path.abspath(cfg_file_path)}{msg}"
+            )
+    return cfg, cfg_file_path
@@ -0,0 +1,178 @@
+# SPDX-FileCopyrightText: 2014-2023 Fredrik Ahlberg, Angus Gratton,
+# Espressif Systems (Shanghai) CO LTD, other contributors as noted.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import os
+import struct
+import time
+
+from .util import FatalError
+
+# Used for resetting into bootloader on Unix-like systems
+if os.name != "nt":
+    import fcntl
+    import termios
+
+    # Constants used for terminal status lines reading/setting.
+    # Taken from pySerial's backend for IO:
+    # https://github.com/pyserial/pyserial/blob/master/serial/serialposix.py
+    TIOCMSET = getattr(termios, "TIOCMSET", 0x5418)
+    TIOCMGET = getattr(termios, "TIOCMGET", 0x5415)
+    TIOCM_DTR = getattr(termios, "TIOCM_DTR", 0x002)
+    TIOCM_RTS = getattr(termios, "TIOCM_RTS", 0x004)
+
+DEFAULT_RESET_DELAY = 0.05  # default time to wait before releasing boot pin after reset
+
+
+class ResetStrategy(object):
+    def __init__(self, port, reset_delay=DEFAULT_RESET_DELAY):
+        self.port = port
+        self.reset_delay = reset_delay
+
+    def __call__():
+        pass
+
+    def _setDTR(self, state):
+        self.port.setDTR(state)
+
+    def _setRTS(self, state):
+        self.port.setRTS(state)
+        # Work-around for adapters on Windows using the usbser.sys driver:
+        # generate a dummy change to DTR so that the set-control-line-state
+        # request is sent with the updated RTS state and the same DTR state
+        self.port.setDTR(self.port.dtr)
+
+    def _setDTRandRTS(self, dtr=False, rts=False):
+        status = struct.unpack(
+            "I", fcntl.ioctl(self.port.fileno(), TIOCMGET, struct.pack("I", 0))
+        )[0]
+        if dtr:
+            status |= TIOCM_DTR
+        else:
+            status &= ~TIOCM_DTR
+        if rts:
+            status |= TIOCM_RTS
+        else:
+            status &= ~TIOCM_RTS
+        fcntl.ioctl(self.port.fileno(), TIOCMSET, struct.pack("I", status))
+
+
+class ClassicReset(ResetStrategy):
+    """
+    Classic reset sequence, sets DTR and RTS lines sequentially.
+    """
+
+    def __call__(self):
+        self._setDTR(False)  # IO0=HIGH
+        self._setRTS(True)  # EN=LOW, chip in reset
+        time.sleep(0.1)
+        self._setDTR(True)  # IO0=LOW
+        self._setRTS(False)  # EN=HIGH, chip out of reset
+        time.sleep(self.reset_delay)
+        self._setDTR(False)  # IO0=HIGH, done
+
+
+class UnixTightReset(ResetStrategy):
+    """
+    UNIX-only reset sequence with custom implementation,
+    which allows setting DTR and RTS lines at the same time.
+    """
+
+    def __call__(self):
+        self._setDTRandRTS(False, False)
+        self._setDTRandRTS(True, True)
+        self._setDTRandRTS(False, True)  # IO0=HIGH & EN=LOW, chip in reset
+        time.sleep(0.1)
+        self._setDTRandRTS(True, False)  # IO0=LOW & EN=HIGH, chip out of reset
+        time.sleep(self.reset_delay)
+        self._setDTRandRTS(False, False)  # IO0=HIGH, done
+        self._setDTR(False)  # Needed in some environments to ensure IO0=HIGH
+
+
+class USBJTAGSerialReset(ResetStrategy):
+    """
+    Custom reset sequence, which is required when the device
+    is connecting via its USB-JTAG-Serial peripheral.
+    """
+
+    def __call__(self):
+        self._setRTS(False)
+        self._setDTR(False)  # Idle
+        time.sleep(0.1)
+        self._setDTR(True)  # Set IO0
+        self._setRTS(False)
+        time.sleep(0.1)
+        self._setRTS(True)  # Reset. Calls inverted to go through (1,1) instead of (0,0)
+        self._setDTR(False)
+        self._setRTS(True)  # RTS set as Windows only propagates DTR on RTS setting
+        time.sleep(0.1)
+        self._setDTR(False)
+        self._setRTS(False)  # Chip out of reset
+
+
+class HardReset(ResetStrategy):
+    """
+    Reset sequence for hard resetting the chip.
+    Can be used to reset out of the bootloader or to restart a running app.
+    """
+
+    def __init__(self, port, uses_usb_otg=False):
+        super().__init__(port)
+        self.uses_usb_otg = uses_usb_otg
+
+    def __call__(self):
+        self._setRTS(True)  # EN->LOW
+        if self.uses_usb_otg:
+            # Give the chip some time to come out of reset,
+            # to be able to handle further DTR/RTS transitions
+            time.sleep(0.2)
+            self._setRTS(False)
+            time.sleep(0.2)
+        else:
+            time.sleep(0.1)
+            self._setRTS(False)
+
+
+class CustomReset(ResetStrategy):
+    """
+    Custom reset strategy defined with a string.
+
+    CustomReset object is created as "rst = CustomReset(port, seq_str)"
+    and can be later executed simply with "rst()"
+
+    The seq_str input string consists of individual commands divided by "|".
+    Commands (e.g. R0) are defined by a code (R) and an argument (0).
+
+    The commands are:
+    D: setDTR - 1=True / 0=False
+    R: setRTS - 1=True / 0=False
+    U: setDTRandRTS (Unix-only) - 0,0 / 0,1 / 1,0 / or 1,1
+    W: Wait (time delay) - positive float number
+
+    e.g.
+    "D0|R1|W0.1|D1|R0|W0.05|D0" represents the ClassicReset strategy
+    "U1,1|U0,1|W0.1|U1,0|W0.05|U0,0" represents the UnixTightReset strategy
+    """
+
+    format_dict = {
+        "D": "self.port.setDTR({})",
+        "R": "self.port.setRTS({})",
+        "W": "time.sleep({})",
+        "U": "self._setDTRandRTS({})",
+    }
+
+    def __call__(self):
+        exec(self.constructed_strategy)
+
+    def __init__(self, port, seq_str):
+        super().__init__(port)
+        self.constructed_strategy = self._parse_string_to_seq(seq_str)
+
+    def _parse_string_to_seq(self, seq_str):
+        try:
+            cmds = seq_str.split("|")
+            fn_calls_list = [self.format_dict[cmd[0]].format(cmd[1:]) for cmd in cmds]
+        except Exception as e:
+            raise FatalError(f'Invalid "custom_reset_sequence" option format: {e}')
+        return "\n".join(fn_calls_list)
@@ -0,0 +1,31 @@
+from .esp32 import ESP32ROM
+from .esp32c2 import ESP32C2ROM
+from .esp32c3 import ESP32C3ROM
+from .esp32c6 import ESP32C6ROM
+from .esp32c6beta import ESP32C6BETAROM
+from .esp32h2 import ESP32H2ROM
+from .esp32h2beta1 import ESP32H2BETA1ROM
+from .esp32h2beta2 import ESP32H2BETA2ROM
+from .esp32s2 import ESP32S2ROM
+from .esp32s3 import ESP32S3ROM
+from .esp32s3beta2 import ESP32S3BETA2ROM
+from .esp8266 import ESP8266ROM
+
+
+CHIP_DEFS = {
+    "esp8266": ESP8266ROM,
+    "esp32": ESP32ROM,
+    "esp32s2": ESP32S2ROM,
+    "esp32s3beta2": ESP32S3BETA2ROM,
+    "esp32s3": ESP32S3ROM,
+    "esp32c3": ESP32C3ROM,
+    "esp32c6beta": ESP32C6BETAROM,
+    "esp32h2beta1": ESP32H2BETA1ROM,
+    "esp32h2beta2": ESP32H2BETA2ROM,
+    "esp32c2": ESP32C2ROM,
+    "esp32c6": ESP32C6ROM,
+    "esp32h2": ESP32H2ROM,
+}
+
+CHIP_LIST = list(CHIP_DEFS.keys())
+ROM_LIST = list(CHIP_DEFS.values())
@@ -0,0 +1,393 @@
+# SPDX-FileCopyrightText: 2014-2022 Fredrik Ahlberg, Angus Gratton,
+# Espressif Systems (Shanghai) CO LTD, other contributors as noted.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import struct
+import time
+
+from ..loader import ESPLoader
+from ..util import FatalError, NotSupportedError
+
+
+class ESP32ROM(ESPLoader):
+    """Access class for ESP32 ROM bootloader"""
+
+    CHIP_NAME = "ESP32"
+    IMAGE_CHIP_ID = 0
+    IS_STUB = False
+
+    FPGA_SLOW_BOOT = True
+
+    CHIP_DETECT_MAGIC_VALUE = [0x00F01D83]
+
+    IROM_MAP_START = 0x400D0000
+    IROM_MAP_END = 0x40400000
+
+    DROM_MAP_START = 0x3F400000
+    DROM_MAP_END = 0x3F800000
+
+    # ESP32 uses a 4 byte status reply
+    STATUS_BYTES_LENGTH = 4
+
+    SPI_REG_BASE = 0x3FF42000
+    SPI_USR_OFFS = 0x1C
+    SPI_USR1_OFFS = 0x20
+    SPI_USR2_OFFS = 0x24
+    SPI_MOSI_DLEN_OFFS = 0x28
+    SPI_MISO_DLEN_OFFS = 0x2C
+    EFUSE_RD_REG_BASE = 0x3FF5A000
+
+    EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_REG = EFUSE_RD_REG_BASE + 0x18
+    EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT = 1 << 7  # EFUSE_RD_DISABLE_DL_ENCRYPT
+
+    EFUSE_SPI_BOOT_CRYPT_CNT_REG = EFUSE_RD_REG_BASE  # EFUSE_BLK0_WDATA0_REG
+    EFUSE_SPI_BOOT_CRYPT_CNT_MASK = 0x7F << 20  # EFUSE_FLASH_CRYPT_CNT
+
+    EFUSE_RD_ABS_DONE_REG = EFUSE_RD_REG_BASE + 0x018
+    EFUSE_RD_ABS_DONE_0_MASK = 1 << 4
+    EFUSE_RD_ABS_DONE_1_MASK = 1 << 5
+
+    DR_REG_SYSCON_BASE = 0x3FF66000
+    APB_CTL_DATE_ADDR = DR_REG_SYSCON_BASE + 0x7C
+    APB_CTL_DATE_V = 0x1
+    APB_CTL_DATE_S = 31
+
+    SPI_W0_OFFS = 0x80
+
+    UART_CLKDIV_REG = 0x3FF40014
+
+    XTAL_CLK_DIVIDER = 1
+
+    RTCCALICFG1 = 0x3FF5F06C
+    TIMERS_RTC_CALI_VALUE = 0x01FFFFFF
+    TIMERS_RTC_CALI_VALUE_S = 7
+
+    FLASH_SIZES = {
+        "1MB": 0x00,
+        "2MB": 0x10,
+        "4MB": 0x20,
+        "8MB": 0x30,
+        "16MB": 0x40,
+        "32MB": 0x50,
+        "64MB": 0x60,
+        "128MB": 0x70,
+    }
+
+    FLASH_FREQUENCY = {
+        "80m": 0xF,
+        "40m": 0x0,
+        "26m": 0x1,
+        "20m": 0x2,
+    }
+
+    BOOTLOADER_FLASH_OFFSET = 0x1000
+
+    OVERRIDE_VDDSDIO_CHOICES = ["1.8V", "1.9V", "OFF"]
+
+    MEMORY_MAP = [
+        [0x00000000, 0x00010000, "PADDING"],
+        [0x3F400000, 0x3F800000, "DROM"],
+        [0x3F800000, 0x3FC00000, "EXTRAM_DATA"],
+        [0x3FF80000, 0x3FF82000, "RTC_DRAM"],
+        [0x3FF90000, 0x40000000, "BYTE_ACCESSIBLE"],
+        [0x3FFAE000, 0x40000000, "DRAM"],
+        [0x3FFE0000, 0x3FFFFFFC, "DIRAM_DRAM"],
+        [0x40000000, 0x40070000, "IROM"],
+        [0x40070000, 0x40078000, "CACHE_PRO"],
+        [0x40078000, 0x40080000, "CACHE_APP"],
+        [0x40080000, 0x400A0000, "IRAM"],
+        [0x400A0000, 0x400BFFFC, "DIRAM_IRAM"],
+        [0x400C0000, 0x400C2000, "RTC_IRAM"],
+        [0x400D0000, 0x40400000, "IROM"],
+        [0x50000000, 0x50002000, "RTC_DATA"],
+    ]
+
+    FLASH_ENCRYPTED_WRITE_ALIGN = 32
+
+    """ Try to read the BLOCK1 (encryption key) and check if it is valid """
+
+    def is_flash_encryption_key_valid(self):
+        """Bit 0 of efuse_rd_disable[3:0] is mapped to BLOCK1
+        this bit is at position 16 in EFUSE_BLK0_RDATA0_REG"""
+        word0 = self.read_efuse(0)
+        rd_disable = (word0 >> 16) & 0x1
+
+        # reading of BLOCK1 is NOT ALLOWED so we assume valid key is programmed
+        if rd_disable:
+            return True
+        else:
+            # reading of BLOCK1 is ALLOWED so we will read and verify for non-zero.
+            # When ESP32 has not generated AES/encryption key in BLOCK1,
+            # the contents will be readable and 0.
+            # If the flash encryption is enabled it is expected to have a valid
+            # non-zero key. We break out on first occurance of non-zero value
+            key_word = [0] * 7
+            for i in range(len(key_word)):
+                key_word[i] = self.read_efuse(14 + i)
+                # key is non-zero so break & return
+                if key_word[i] != 0:
+                    return True
+            return False
+
+    def get_flash_crypt_config(self):
+        """For flash encryption related commands we need to make sure
+        user has programmed all the relevant efuse correctly so before
+        writing encrypted write_flash_encrypt esptool will verify the values
+        of flash_crypt_config to be non zero if they are not read
+        protected. If the values are zero a warning will be printed
+
+        bit 3 in efuse_rd_disable[3:0] is mapped to flash_crypt_config
+        this bit is at position 19 in EFUSE_BLK0_RDATA0_REG"""
+        word0 = self.read_efuse(0)
+        rd_disable = (word0 >> 19) & 0x1
+
+        if rd_disable == 0:
+            """we can read the flash_crypt_config efuse value
+            so go & read it (EFUSE_BLK0_RDATA5_REG[31:28])"""
+            word5 = self.read_efuse(5)
+            word5 = (word5 >> 28) & 0xF
+            return word5
+        else:
+            # if read of the efuse is disabled we assume it is set correctly
+            return 0xF
+
+    def get_encrypted_download_disabled(self):
+        return (
+            self.read_reg(self.EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_REG)
+            & self.EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT
+        )
+
+    def get_flash_encryption_enabled(self):
+        flash_crypt_cnt = (
+            self.read_reg(self.EFUSE_SPI_BOOT_CRYPT_CNT_REG)
+            & self.EFUSE_SPI_BOOT_CRYPT_CNT_MASK
+        )
+        # Flash encryption enabled when odd number of bits are set
+        return bin(flash_crypt_cnt).count("1") & 1 != 0
+
+    def get_secure_boot_enabled(self):
+        efuses = self.read_reg(self.EFUSE_RD_ABS_DONE_REG)
+        rev = self.get_chip_revision()
+        return efuses & self.EFUSE_RD_ABS_DONE_0_MASK or (
+            rev >= 300 and efuses & self.EFUSE_RD_ABS_DONE_1_MASK
+        )
+
+    def get_pkg_version(self):
+        word3 = self.read_efuse(3)
+        pkg_version = (word3 >> 9) & 0x07
+        pkg_version += ((word3 >> 2) & 0x1) << 3
+        return pkg_version
+
+    def get_chip_revision(self):
+        return self.get_major_chip_version() * 100 + self.get_minor_chip_version()
+
+    def get_minor_chip_version(self):
+        return (self.read_efuse(5) >> 24) & 0x3
+
+    def get_major_chip_version(self):
+        rev_bit0 = (self.read_efuse(3) >> 15) & 0x1
+        rev_bit1 = (self.read_efuse(5) >> 20) & 0x1
+        apb_ctl_date = self.read_reg(self.APB_CTL_DATE_ADDR)
+        rev_bit2 = (apb_ctl_date >> self.APB_CTL_DATE_S) & self.APB_CTL_DATE_V
+        combine_value = (rev_bit2 << 2) | (rev_bit1 << 1) | rev_bit0
+
+        revision = {
+            0: 0,
+            1: 1,
+            3: 2,
+            7: 3,
+        }.get(combine_value, 0)
+        return revision
+
+    def get_chip_description(self):
+        pkg_version = self.get_pkg_version()
+        major_rev = self.get_major_chip_version()
+        minor_rev = self.get_minor_chip_version()
+        rev3 = major_rev == 3
+        single_core = self.read_efuse(3) & (1 << 0)  # CHIP_VER DIS_APP_CPU
+
+        chip_name = {
+            0: "ESP32-S0WDQ6" if single_core else "ESP32-D0WDQ6",
+            1: "ESP32-S0WD" if single_core else "ESP32-D0WD",
+            2: "ESP32-D2WD",
+            4: "ESP32-U4WDH",
+            5: "ESP32-PICO-V3" if rev3 else "ESP32-PICO-D4",
+            6: "ESP32-PICO-V3-02",
+            7: "ESP32-D0WDR2-V3",
+        }.get(pkg_version, "unknown ESP32")
+
+        # ESP32-D0WD-V3, ESP32-D0WDQ6-V3
+        if chip_name.startswith("ESP32-D0WD") and rev3:
+            chip_name += "-V3"
+
+        return f"{chip_name} (revision v{major_rev}.{minor_rev})"
+
+    def get_chip_features(self):
+        features = ["WiFi"]
+        word3 = self.read_efuse(3)
+
+        # names of variables in this section are lowercase
+        #  versions of EFUSE names as documented in TRM and
+        # ESP-IDF efuse_reg.h
+
+        chip_ver_dis_bt = word3 & (1 << 1)
+        if chip_ver_dis_bt == 0:
+            features += ["BT"]
+
+        chip_ver_dis_app_cpu = word3 & (1 << 0)
+        if chip_ver_dis_app_cpu:
+            features += ["Single Core"]
+        else:
+            features += ["Dual Core"]
+
+        chip_cpu_freq_rated = word3 & (1 << 13)
+        if chip_cpu_freq_rated:
+            chip_cpu_freq_low = word3 & (1 << 12)
+            if chip_cpu_freq_low:
+                features += ["160MHz"]
+            else:
+                features += ["240MHz"]
+
+        pkg_version = self.get_pkg_version()
+        if pkg_version in [2, 4, 5, 6]:
+            features += ["Embedded Flash"]
+
+        if pkg_version == 6:
+            features += ["Embedded PSRAM"]
+
+        word4 = self.read_efuse(4)
+        adc_vref = (word4 >> 8) & 0x1F
+        if adc_vref:
+            features += ["VRef calibration in efuse"]
+
+        blk3_part_res = word3 >> 14 & 0x1
+        if blk3_part_res:
+            features += ["BLK3 partially reserved"]
+
+        word6 = self.read_efuse(6)
+        coding_scheme = word6 & 0x3
+        features += [
+            "Coding Scheme %s"
+            % {0: "None", 1: "3/4", 2: "Repeat (UNSUPPORTED)", 3: "Invalid"}[
+                coding_scheme
+            ]
+        ]
+
+        return features
+
+    def read_efuse(self, n):
+        """Read the nth word of the ESP3x EFUSE region."""
+        return self.read_reg(self.EFUSE_RD_REG_BASE + (4 * n))
+
+    def chip_id(self):
+        raise NotSupportedError(self, "chip_id")
+
+    def read_mac(self):
+        """Read MAC from EFUSE region"""
+        words = [self.read_efuse(2), self.read_efuse(1)]
+        bitstring = struct.pack(">II", *words)
+        bitstring = bitstring[2:8]  # trim the 2 byte CRC
+        return tuple(bitstring)
+
+    def get_erase_size(self, offset, size):
+        return size
+
+    def override_vddsdio(self, new_voltage):
+        new_voltage = new_voltage.upper()
+        if new_voltage not in self.OVERRIDE_VDDSDIO_CHOICES:
+            raise FatalError(
+                "The only accepted VDDSDIO overrides are '1.8V', '1.9V' and 'OFF'"
+            )
+        RTC_CNTL_SDIO_CONF_REG = 0x3FF48074
+        RTC_CNTL_XPD_SDIO_REG = 1 << 31
+        RTC_CNTL_DREFH_SDIO_M = 3 << 29
+        RTC_CNTL_DREFM_SDIO_M = 3 << 27
+        RTC_CNTL_DREFL_SDIO_M = 3 << 25
+        # RTC_CNTL_SDIO_TIEH = (1 << 23)
+        # not used here, setting TIEH=1 would set 3.3V output,
+        # not safe for esptool.py to do
+        RTC_CNTL_SDIO_FORCE = 1 << 22
+        RTC_CNTL_SDIO_PD_EN = 1 << 21
+
+        reg_val = RTC_CNTL_SDIO_FORCE  # override efuse setting
+        reg_val |= RTC_CNTL_SDIO_PD_EN
+        if new_voltage != "OFF":
+            reg_val |= RTC_CNTL_XPD_SDIO_REG  # enable internal LDO
+        if new_voltage == "1.9V":
+            reg_val |= (
+                RTC_CNTL_DREFH_SDIO_M | RTC_CNTL_DREFM_SDIO_M | RTC_CNTL_DREFL_SDIO_M
+            )  # boost voltage
+        self.write_reg(RTC_CNTL_SDIO_CONF_REG, reg_val)
+        print("VDDSDIO regulator set to %s" % new_voltage)
+
+    def read_flash_slow(self, offset, length, progress_fn):
+        BLOCK_LEN = 64  # ROM read limit per command (this limit is why it's so slow)
+
+        data = b""
+        while len(data) < length:
+            block_len = min(BLOCK_LEN, length - len(data))
+            r = self.check_command(
+                "read flash block",
+                self.ESP_READ_FLASH_SLOW,
+                struct.pack("<II", offset + len(data), block_len),
+            )
+            if len(r) < block_len:
+                raise FatalError(
+                    "Expected %d byte block, got %d bytes. Serial errors?"
+                    % (block_len, len(r))
+                )
+            # command always returns 64 byte buffer,
+            # regardless of how many bytes were actually read from flash
+            data += r[:block_len]
+            if progress_fn and (len(data) % 1024 == 0 or len(data) == length):
+                progress_fn(len(data), length)
+        return data
+
+    def get_rom_cal_crystal_freq(self):
+        """
+        Get the crystal frequency calculated by the ROM
+        """
+        # - Simulate the calculation in the ROM to get the XTAL frequency
+        #   calculated by the ROM
+
+        cali_val = (
+            self.read_reg(self.RTCCALICFG1) >> self.TIMERS_RTC_CALI_VALUE_S
+        ) & self.TIMERS_RTC_CALI_VALUE
+        clk_8M_freq = self.read_efuse(4) & (0xFF)  # EFUSE_RD_CK8M_FREQ
+        rom_calculated_freq = cali_val * 15625 * clk_8M_freq / 40
+        return rom_calculated_freq
+
+    def change_baud(self, baud):
+        # It's a workaround to avoid esp32 CK_8M frequency drift.
+        rom_calculated_freq = self.get_rom_cal_crystal_freq()
+        valid_freq = 40000000 if rom_calculated_freq > 33000000 else 26000000
+        false_rom_baud = int(baud * rom_calculated_freq // valid_freq)
+
+        print(f"Changing baud rate to {baud}")
+        self.command(self.ESP_CHANGE_BAUDRATE, struct.pack("<II", false_rom_baud, 0))
+        print("Changed.")
+        self._set_port_baudrate(baud)
+        time.sleep(0.05)  # get rid of garbage sent during baud rate change
+        self.flush_input()
+
+
+class ESP32StubLoader(ESP32ROM):
+    """Access class for ESP32 stub loader, runs on top of ROM."""
+
+    FLASH_WRITE_SIZE = 0x4000  # matches MAX_WRITE_BLOCK in stub_loader.c
+    STATUS_BYTES_LENGTH = 2  # same as ESP8266, different to ESP32 ROM
+    IS_STUB = True
+
+    def __init__(self, rom_loader):
+        self.secure_download_mode = rom_loader.secure_download_mode
+        self._port = rom_loader._port
+        self._trace_enabled = rom_loader._trace_enabled
+        self.cache = rom_loader.cache
+        self.flush_input()  # resets _slip_reader
+
+    def change_baud(self, baud):
+        ESPLoader.change_baud(self, baud)
+
+
+ESP32ROM.STUB_CLASS = ESP32StubLoader
@@ -0,0 +1,165 @@
+# SPDX-FileCopyrightText: 2014-2022 Fredrik Ahlberg, Angus Gratton,
+# Espressif Systems (Shanghai) CO LTD, other contributors as noted.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import struct
+import time
+
+from .esp32c3 import ESP32C3ROM
+from ..loader import ESPLoader
+
+
+class ESP32C2ROM(ESP32C3ROM):
+    CHIP_NAME = "ESP32-C2"
+    IMAGE_CHIP_ID = 12
+
+    IROM_MAP_START = 0x42000000
+    IROM_MAP_END = 0x42400000
+    DROM_MAP_START = 0x3C000000
+    DROM_MAP_END = 0x3C400000
+
+    # Magic value for ESP32C2 ECO0 and ECO1 respectively
+    CHIP_DETECT_MAGIC_VALUE = [0x6F51306F, 0x7C41A06F]
+
+    EFUSE_BASE = 0x60008800
+    EFUSE_BLOCK2_ADDR = EFUSE_BASE + 0x040
+    MAC_EFUSE_REG = EFUSE_BASE + 0x040
+
+    EFUSE_SECURE_BOOT_EN_REG = EFUSE_BASE + 0x30
+    EFUSE_SECURE_BOOT_EN_MASK = 1 << 21
+
+    EFUSE_SPI_BOOT_CRYPT_CNT_REG = EFUSE_BASE + 0x30
+    EFUSE_SPI_BOOT_CRYPT_CNT_MASK = 0x7 << 18
+
+    EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_REG = EFUSE_BASE + 0x30
+    EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT = 1 << 6
+
+    EFUSE_XTS_KEY_LENGTH_256_REG = EFUSE_BASE + 0x30
+    EFUSE_XTS_KEY_LENGTH_256 = 1 << 10
+
+    EFUSE_BLOCK_KEY0_REG = EFUSE_BASE + 0x60
+
+    EFUSE_RD_DIS_REG = EFUSE_BASE + 0x30
+    EFUSE_RD_DIS = 3
+
+    FLASH_FREQUENCY = {
+        "60m": 0xF,
+        "30m": 0x0,
+        "20m": 0x1,
+        "15m": 0x2,
+    }
+
+    MEMORY_MAP = [
+        [0x00000000, 0x00010000, "PADDING"],
+        [0x3C000000, 0x3C400000, "DROM"],
+        [0x3FCA0000, 0x3FCE0000, "DRAM"],
+        [0x3FC88000, 0x3FD00000, "BYTE_ACCESSIBLE"],
+        [0x3FF00000, 0x3FF50000, "DROM_MASK"],
+        [0x40000000, 0x40090000, "IROM_MASK"],
+        [0x42000000, 0x42400000, "IROM"],
+        [0x4037C000, 0x403C0000, "IRAM"],
+    ]
+
+    def get_pkg_version(self):
+        num_word = 1
+        return (self.read_reg(self.EFUSE_BLOCK2_ADDR + (4 * num_word)) >> 22) & 0x07
+
+    def get_chip_description(self):
+        chip_name = {
+            0: "ESP32-C2",
+            1: "ESP32-C2",
+        }.get(self.get_pkg_version(), "unknown ESP32-C2")
+        major_rev = self.get_major_chip_version()
+        minor_rev = self.get_minor_chip_version()
+        return f"{chip_name} (revision v{major_rev}.{minor_rev})"
+
+    def get_minor_chip_version(self):
+        num_word = 1
+        return (self.read_reg(self.EFUSE_BLOCK2_ADDR + (4 * num_word)) >> 16) & 0xF
+
+    def get_major_chip_version(self):
+        num_word = 1
+        return (self.read_reg(self.EFUSE_BLOCK2_ADDR + (4 * num_word)) >> 20) & 0x3
+
+    def get_crystal_freq(self):
+        # The crystal detection algorithm of ESP32/ESP8266 works for ESP32-C2 as well.
+        return ESPLoader.get_crystal_freq(self)
+
+    def change_baud(self, baud):
+        rom_with_26M_XTAL = not self.IS_STUB and self.get_crystal_freq() == 26
+        if rom_with_26M_XTAL:
+            # The code is copied over from ESPLoader.change_baud().
+            # Probably this is just a temporary solution until the next chip revision.
+
+            # The ROM code thinks it uses a 40 MHz XTAL. Recompute the baud rate
+            # in order to trick the ROM code to set the correct baud rate for
+            # a 26 MHz XTAL.
+            false_rom_baud = baud * 40 // 26
+
+            print(f"Changing baud rate to {baud}")
+            self.command(
+                self.ESP_CHANGE_BAUDRATE, struct.pack("<II", false_rom_baud, 0)
+            )
+            print("Changed.")
+            self._set_port_baudrate(baud)
+            time.sleep(0.05)  # get rid of garbage sent during baud rate change
+            self.flush_input()
+        else:
+            ESPLoader.change_baud(self, baud)
+
+    def _post_connect(self):
+        # ESP32C2 ECO0 is no longer supported by the flasher stub
+        if self.get_chip_revision() == 0:
+            self.stub_is_disabled = True
+            self.IS_STUB = False
+
+    """ Try to read (encryption key) and check if it is valid """
+
+    def is_flash_encryption_key_valid(self):
+        key_len_256 = (
+            self.read_reg(self.EFUSE_XTS_KEY_LENGTH_256_REG)
+            & self.EFUSE_XTS_KEY_LENGTH_256
+        )
+
+        word0 = self.read_reg(self.EFUSE_RD_DIS_REG) & self.EFUSE_RD_DIS
+        rd_disable = word0 == 3 if key_len_256 else word0 == 1
+
+        # reading of BLOCK3 is NOT ALLOWED so we assume valid key is programmed
+        if rd_disable:
+            return True
+        else:
+            # reading of BLOCK3 is ALLOWED so we will read and verify for non-zero.
+            # When chip has not generated AES/encryption key in BLOCK3,
+            # the contents will be readable and 0.
+            # If the flash encryption is enabled it is expected to have a valid
+            # non-zero key. We break out on first occurance of non-zero value
+            key_word = [0] * 7 if key_len_256 else [0] * 3
+            for i in range(len(key_word)):
+                key_word[i] = self.read_reg(self.EFUSE_BLOCK_KEY0_REG + i * 4)
+                # key is non-zero so break & return
+                if key_word[i] != 0:
+                    return True
+            return False
+
+
+class ESP32C2StubLoader(ESP32C2ROM):
+    """Access class for ESP32C2 stub loader, runs on top of ROM.
+
+    (Basically the same as ESP32StubLoader, but different base class.
+    Can possibly be made into a mixin.)
+    """
+
+    FLASH_WRITE_SIZE = 0x4000  # matches MAX_WRITE_BLOCK in stub_loader.c
+    STATUS_BYTES_LENGTH = 2  # same as ESP8266, different to ESP32 ROM
+    IS_STUB = True
+
+    def __init__(self, rom_loader):
+        self.secure_download_mode = rom_loader.secure_download_mode
+        self._port = rom_loader._port
+        self._trace_enabled = rom_loader._trace_enabled
+        self.cache = rom_loader.cache
+        self.flush_input()  # resets _slip_reader
+
+
+ESP32C2ROM.STUB_CLASS = ESP32C2StubLoader
@@ -0,0 +1,210 @@
+# SPDX-FileCopyrightText: 2014-2022 Fredrik Ahlberg, Angus Gratton,
+# Espressif Systems (Shanghai) CO LTD, other contributors as noted.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import struct
+
+from .esp32 import ESP32ROM
+from ..loader import ESPLoader
+from ..util import FatalError, NotImplementedInROMError
+
+
+class ESP32C3ROM(ESP32ROM):
+    CHIP_NAME = "ESP32-C3"
+    IMAGE_CHIP_ID = 5
+
+    FPGA_SLOW_BOOT = False
+
+    IROM_MAP_START = 0x42000000
+    IROM_MAP_END = 0x42800000
+    DROM_MAP_START = 0x3C000000
+    DROM_MAP_END = 0x3C800000
+
+    SPI_REG_BASE = 0x60002000
+    SPI_USR_OFFS = 0x18
+    SPI_USR1_OFFS = 0x1C
+    SPI_USR2_OFFS = 0x20
+    SPI_MOSI_DLEN_OFFS = 0x24
+    SPI_MISO_DLEN_OFFS = 0x28
+    SPI_W0_OFFS = 0x58
+
+    BOOTLOADER_FLASH_OFFSET = 0x0
+
+    # Magic value for ESP32C3 eco 1+2 and ESP32C3 eco3 respectivly
+    CHIP_DETECT_MAGIC_VALUE = [0x6921506F, 0x1B31506F]
+
+    UART_DATE_REG_ADDR = 0x60000000 + 0x7C
+
+    UART_CLKDIV_REG = 0x60000014
+
+    EFUSE_BASE = 0x60008800
+    EFUSE_BLOCK1_ADDR = EFUSE_BASE + 0x044
+    MAC_EFUSE_REG = EFUSE_BASE + 0x044
+
+    EFUSE_RD_REG_BASE = EFUSE_BASE + 0x030  # BLOCK0 read base address
+
+    EFUSE_PURPOSE_KEY0_REG = EFUSE_BASE + 0x34
+    EFUSE_PURPOSE_KEY0_SHIFT = 24
+    EFUSE_PURPOSE_KEY1_REG = EFUSE_BASE + 0x34
+    EFUSE_PURPOSE_KEY1_SHIFT = 28
+    EFUSE_PURPOSE_KEY2_REG = EFUSE_BASE + 0x38
+    EFUSE_PURPOSE_KEY2_SHIFT = 0
+    EFUSE_PURPOSE_KEY3_REG = EFUSE_BASE + 0x38
+    EFUSE_PURPOSE_KEY3_SHIFT = 4
+    EFUSE_PURPOSE_KEY4_REG = EFUSE_BASE + 0x38
+    EFUSE_PURPOSE_KEY4_SHIFT = 8
+    EFUSE_PURPOSE_KEY5_REG = EFUSE_BASE + 0x38
+    EFUSE_PURPOSE_KEY5_SHIFT = 12
+
+    EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_REG = EFUSE_RD_REG_BASE
+    EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT = 1 << 20
+
+    EFUSE_SPI_BOOT_CRYPT_CNT_REG = EFUSE_BASE + 0x034
+    EFUSE_SPI_BOOT_CRYPT_CNT_MASK = 0x7 << 18
+
+    EFUSE_SECURE_BOOT_EN_REG = EFUSE_BASE + 0x038
+    EFUSE_SECURE_BOOT_EN_MASK = 1 << 20
+
+    PURPOSE_VAL_XTS_AES128_KEY = 4
+
+    SUPPORTS_ENCRYPTED_FLASH = True
+
+    FLASH_ENCRYPTED_WRITE_ALIGN = 16
+
+    UARTDEV_BUF_NO = 0x3FCDF07C  # Variable in ROM .bss which indicates the port in use
+    UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3  # The above var when USB-JTAG/Serial is used
+
+    RTC_CNTL_WDT_WKEY = 0x50D83AA1
+    RTCCNTL_BASE_REG = 0x60008000
+    RTC_CNTL_WDTCONFIG0_REG = RTCCNTL_BASE_REG + 0x0090
+    RTC_CNTL_WDTWPROTECT_REG = RTCCNTL_BASE_REG + 0x00A8
+
+    MEMORY_MAP = [
+        [0x00000000, 0x00010000, "PADDING"],
+        [0x3C000000, 0x3C800000, "DROM"],
+        [0x3FC80000, 0x3FCE0000, "DRAM"],
+        [0x3FC88000, 0x3FD00000, "BYTE_ACCESSIBLE"],
+        [0x3FF00000, 0x3FF20000, "DROM_MASK"],
+        [0x40000000, 0x40060000, "IROM_MASK"],
+        [0x42000000, 0x42800000, "IROM"],
+        [0x4037C000, 0x403E0000, "IRAM"],
+        [0x50000000, 0x50002000, "RTC_IRAM"],
+        [0x50000000, 0x50002000, "RTC_DRAM"],
+        [0x600FE000, 0x60100000, "MEM_INTERNAL2"],
+    ]
+
+    def get_pkg_version(self):
+        num_word = 3
+        return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 21) & 0x07
+
+    def get_minor_chip_version(self):
+        hi_num_word = 5
+        hi = (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * hi_num_word)) >> 23) & 0x01
+        low_num_word = 3
+        low = (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * low_num_word)) >> 18) & 0x07
+        return (hi << 3) + low
+
+    def get_major_chip_version(self):
+        num_word = 5
+        return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 24) & 0x03
+
+    def get_chip_description(self):
+        chip_name = {
+            0: "ESP32-C3",
+        }.get(self.get_pkg_version(), "unknown ESP32-C3")
+        major_rev = self.get_major_chip_version()
+        minor_rev = self.get_minor_chip_version()
+        return f"{chip_name} (revision v{major_rev}.{minor_rev})"
+
+    def get_chip_features(self):
+        return ["WiFi", "BLE"]
+
+    def get_crystal_freq(self):
+        # ESP32C3 XTAL is fixed to 40MHz
+        return 40
+
+    def override_vddsdio(self, new_voltage):
+        raise NotImplementedInROMError(
+            "VDD_SDIO overrides are not supported for ESP32-C3"
+        )
+
+    def read_mac(self):
+        mac0 = self.read_reg(self.MAC_EFUSE_REG)
+        mac1 = self.read_reg(self.MAC_EFUSE_REG + 4)  # only bottom 16 bits are MAC
+        bitstring = struct.pack(">II", mac1, mac0)[2:]
+        return tuple(bitstring)
+
+    def get_flash_crypt_config(self):
+        return None  # doesn't exist on ESP32-C3
+
+    def get_secure_boot_enabled(self):
+        return (
+            self.read_reg(self.EFUSE_SECURE_BOOT_EN_REG)
+            & self.EFUSE_SECURE_BOOT_EN_MASK
+        )
+
+    def get_key_block_purpose(self, key_block):
+        if key_block < 0 or key_block > 5:
+            raise FatalError("Valid key block numbers must be in range 0-5")
+
+        reg, shift = [
+            (self.EFUSE_PURPOSE_KEY0_REG, self.EFUSE_PURPOSE_KEY0_SHIFT),
+            (self.EFUSE_PURPOSE_KEY1_REG, self.EFUSE_PURPOSE_KEY1_SHIFT),
+            (self.EFUSE_PURPOSE_KEY2_REG, self.EFUSE_PURPOSE_KEY2_SHIFT),
+            (self.EFUSE_PURPOSE_KEY3_REG, self.EFUSE_PURPOSE_KEY3_SHIFT),
+            (self.EFUSE_PURPOSE_KEY4_REG, self.EFUSE_PURPOSE_KEY4_SHIFT),
+            (self.EFUSE_PURPOSE_KEY5_REG, self.EFUSE_PURPOSE_KEY5_SHIFT),
+        ][key_block]
+        return (self.read_reg(reg) >> shift) & 0xF
+
+    def is_flash_encryption_key_valid(self):
+        # Need to see an AES-128 key
+        purposes = [self.get_key_block_purpose(b) for b in range(6)]
+
+        return any(p == self.PURPOSE_VAL_XTS_AES128_KEY for p in purposes)
+
+    def change_baud(self, baud):
+        ESPLoader.change_baud(self, baud)
+
+    def uses_usb_jtag_serial(self):
+        """
+        Check the UARTDEV_BUF_NO register to see if USB-JTAG/Serial is being used
+        """
+        if self.secure_download_mode:
+            return False  # Can't detect USB-JTAG/Serial in secure download mode
+        return self.get_uart_no() == self.UARTDEV_BUF_NO_USB_JTAG_SERIAL
+
+    def disable_rtc_watchdog(self):
+        # When USB-JTAG/Serial is used, the RTC watchdog is not reset
+        # and can then reset the board during flashing. Disable it.
+        if self.uses_usb_jtag_serial():
+            self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_WDT_WKEY)
+            self.write_reg(self.RTC_CNTL_WDTCONFIG0_REG, 0)
+            self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, 0)
+
+    def _post_connect(self):
+        if not self.sync_stub_detected:  # Don't run if stub is reused
+            self.disable_rtc_watchdog()
+
+
+class ESP32C3StubLoader(ESP32C3ROM):
+    """Access class for ESP32C3 stub loader, runs on top of ROM.
+
+    (Basically the same as ESP32StubLoader, but different base class.
+    Can possibly be made into a mixin.)
+    """
+
+    FLASH_WRITE_SIZE = 0x4000  # matches MAX_WRITE_BLOCK in stub_loader.c
+    STATUS_BYTES_LENGTH = 2  # same as ESP8266, different to ESP32 ROM
+    IS_STUB = True
+
+    def __init__(self, rom_loader):
+        self.secure_download_mode = rom_loader.secure_download_mode
+        self._port = rom_loader._port
+        self._trace_enabled = rom_loader._trace_enabled
+        self.cache = rom_loader.cache
+        self.flush_input()  # resets _slip_reader
+
+
+ESP32C3ROM.STUB_CLASS = ESP32C3StubLoader
@@ -0,0 +1,189 @@
+# SPDX-FileCopyrightText: 2022 Fredrik Ahlberg, Angus Gratton,
+# Espressif Systems (Shanghai) CO LTD, other contributors as noted.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import struct
+
+from .esp32c3 import ESP32C3ROM
+from ..util import FatalError, NotImplementedInROMError
+
+
+class ESP32C6ROM(ESP32C3ROM):
+    CHIP_NAME = "ESP32-C6"
+    IMAGE_CHIP_ID = 13
+
+    FPGA_SLOW_BOOT = False
+
+    IROM_MAP_START = 0x42000000
+    IROM_MAP_END = 0x42800000
+    DROM_MAP_START = 0x42800000
+    DROM_MAP_END = 0x43000000
+
+    BOOTLOADER_FLASH_OFFSET = 0x0
+
+    # Magic value for ESP32C6
+    CHIP_DETECT_MAGIC_VALUE = [0x2CE0806F]
+
+    SPI_REG_BASE = 0x60003000
+    SPI_USR_OFFS = 0x18
+    SPI_USR1_OFFS = 0x1C
+    SPI_USR2_OFFS = 0x20
+    SPI_MOSI_DLEN_OFFS = 0x24
+    SPI_MISO_DLEN_OFFS = 0x28
+    SPI_W0_OFFS = 0x58
+
+    UART_DATE_REG_ADDR = 0x60000000 + 0x7C
+
+    EFUSE_BASE = 0x600B0800
+    EFUSE_BLOCK1_ADDR = EFUSE_BASE + 0x044
+    MAC_EFUSE_REG = EFUSE_BASE + 0x044
+
+    EFUSE_RD_REG_BASE = EFUSE_BASE + 0x030  # BLOCK0 read base address
+
+    EFUSE_PURPOSE_KEY0_REG = EFUSE_BASE + 0x34
+    EFUSE_PURPOSE_KEY0_SHIFT = 24
+    EFUSE_PURPOSE_KEY1_REG = EFUSE_BASE + 0x34
+    EFUSE_PURPOSE_KEY1_SHIFT = 28
+    EFUSE_PURPOSE_KEY2_REG = EFUSE_BASE + 0x38
+    EFUSE_PURPOSE_KEY2_SHIFT = 0
+    EFUSE_PURPOSE_KEY3_REG = EFUSE_BASE + 0x38
+    EFUSE_PURPOSE_KEY3_SHIFT = 4
+    EFUSE_PURPOSE_KEY4_REG = EFUSE_BASE + 0x38
+    EFUSE_PURPOSE_KEY4_SHIFT = 8
+    EFUSE_PURPOSE_KEY5_REG = EFUSE_BASE + 0x38
+    EFUSE_PURPOSE_KEY5_SHIFT = 12
+
+    EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_REG = EFUSE_RD_REG_BASE
+    EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT = 1 << 20
+
+    EFUSE_SPI_BOOT_CRYPT_CNT_REG = EFUSE_BASE + 0x034
+    EFUSE_SPI_BOOT_CRYPT_CNT_MASK = 0x7 << 18
+
+    EFUSE_SECURE_BOOT_EN_REG = EFUSE_BASE + 0x038
+    EFUSE_SECURE_BOOT_EN_MASK = 1 << 20
+
+    PURPOSE_VAL_XTS_AES128_KEY = 4
+
+    SUPPORTS_ENCRYPTED_FLASH = True
+
+    FLASH_ENCRYPTED_WRITE_ALIGN = 16
+
+    UARTDEV_BUF_NO = 0x4087F580  # Variable in ROM .bss which indicates the port in use
+    UARTDEV_BUF_NO_USB_JTAG_SERIAL = 3  # The above var when USB-JTAG/Serial is used
+
+    DR_REG_LP_WDT_BASE = 0x600B1C00
+    RTC_CNTL_WDTCONFIG0_REG = DR_REG_LP_WDT_BASE + 0x0  # LP_WDT_RWDT_CONFIG0_REG
+    RTC_CNTL_WDTWPROTECT_REG = DR_REG_LP_WDT_BASE + 0x0018  # LP_WDT_RWDT_WPROTECT_REG
+
+    FLASH_FREQUENCY = {
+        "80m": 0x0,  # workaround for wrong mspi HS div value in ROM
+        "40m": 0x0,
+        "20m": 0x2,
+    }
+
+    MEMORY_MAP = [
+        [0x00000000, 0x00010000, "PADDING"],
+        [0x42800000, 0x43000000, "DROM"],
+        [0x40800000, 0x40880000, "DRAM"],
+        [0x40800000, 0x40880000, "BYTE_ACCESSIBLE"],
+        [0x4004AC00, 0x40050000, "DROM_MASK"],
+        [0x40000000, 0x4004AC00, "IROM_MASK"],
+        [0x42000000, 0x42800000, "IROM"],
+        [0x40800000, 0x40880000, "IRAM"],
+        [0x50000000, 0x50004000, "RTC_IRAM"],
+        [0x50000000, 0x50004000, "RTC_DRAM"],
+        [0x600FE000, 0x60100000, "MEM_INTERNAL2"],
+    ]
+
+    def get_pkg_version(self):
+        num_word = 3
+        return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 21) & 0x07
+
+    def get_minor_chip_version(self):
+        hi_num_word = 5
+        hi = (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * hi_num_word)) >> 23) & 0x01
+        low_num_word = 3
+        low = (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * low_num_word)) >> 18) & 0x07
+        return (hi << 3) + low
+
+    def get_major_chip_version(self):
+        num_word = 5
+        return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 24) & 0x03
+
+    def get_chip_description(self):
+        chip_name = {
+            0: "ESP32-C6",
+        }.get(self.get_pkg_version(), "unknown ESP32-C6")
+        major_rev = self.get_major_chip_version()
+        minor_rev = self.get_minor_chip_version()
+        return f"{chip_name} (revision v{major_rev}.{minor_rev})"
+
+    def get_chip_features(self):
+        return ["WiFi 6", "BT 5", "IEEE802.15.4"]
+
+    def get_crystal_freq(self):
+        # ESP32C6 XTAL is fixed to 40MHz
+        return 40
+
+    def override_vddsdio(self, new_voltage):
+        raise NotImplementedInROMError(
+            "VDD_SDIO overrides are not supported for ESP32-C6"
+        )
+
+    def read_mac(self):
+        mac0 = self.read_reg(self.MAC_EFUSE_REG)
+        mac1 = self.read_reg(self.MAC_EFUSE_REG + 4)  # only bottom 16 bits are MAC
+        bitstring = struct.pack(">II", mac1, mac0)[2:]
+        return tuple(bitstring)
+
+    def get_flash_crypt_config(self):
+        return None  # doesn't exist on ESP32-C6
+
+    def get_secure_boot_enabled(self):
+        return (
+            self.read_reg(self.EFUSE_SECURE_BOOT_EN_REG)
+            & self.EFUSE_SECURE_BOOT_EN_MASK
+        )
+
+    def get_key_block_purpose(self, key_block):
+        if key_block < 0 or key_block > 5:
+            raise FatalError("Valid key block numbers must be in range 0-5")
+
+        reg, shift = [
+            (self.EFUSE_PURPOSE_KEY0_REG, self.EFUSE_PURPOSE_KEY0_SHIFT),
+            (self.EFUSE_PURPOSE_KEY1_REG, self.EFUSE_PURPOSE_KEY1_SHIFT),
+            (self.EFUSE_PURPOSE_KEY2_REG, self.EFUSE_PURPOSE_KEY2_SHIFT),
+            (self.EFUSE_PURPOSE_KEY3_REG, self.EFUSE_PURPOSE_KEY3_SHIFT),
+            (self.EFUSE_PURPOSE_KEY4_REG, self.EFUSE_PURPOSE_KEY4_SHIFT),
+            (self.EFUSE_PURPOSE_KEY5_REG, self.EFUSE_PURPOSE_KEY5_SHIFT),
+        ][key_block]
+        return (self.read_reg(reg) >> shift) & 0xF
+
+    def is_flash_encryption_key_valid(self):
+        # Need to see an AES-128 key
+        purposes = [self.get_key_block_purpose(b) for b in range(6)]
+
+        return any(p == self.PURPOSE_VAL_XTS_AES128_KEY for p in purposes)
+
+
+class ESP32C6StubLoader(ESP32C6ROM):
+    """Access class for ESP32C6 stub loader, runs on top of ROM.
+
+    (Basically the same as ESP32StubLoader, but different base class.
+    Can possibly be made into a mixin.)
+    """
+
+    FLASH_WRITE_SIZE = 0x4000  # matches MAX_WRITE_BLOCK in stub_loader.c
+    STATUS_BYTES_LENGTH = 2  # same as ESP8266, different to ESP32 ROM
+    IS_STUB = True
+
+    def __init__(self, rom_loader):
+        self.secure_download_mode = rom_loader.secure_download_mode
+        self._port = rom_loader._port
+        self._trace_enabled = rom_loader._trace_enabled
+        self.cache = rom_loader.cache
+        self.flush_input()  # resets _slip_reader
+
+
+ESP32C6ROM.STUB_CLASS = ESP32C6StubLoader
@@ -0,0 +1,26 @@
+# SPDX-FileCopyrightText: 2014-2022 Fredrik Ahlberg, Angus Gratton,
+# Espressif Systems (Shanghai) CO LTD, other contributors as noted.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from .esp32c3 import ESP32C3ROM
+
+
+class ESP32C6BETAROM(ESP32C3ROM):
+    CHIP_NAME = "ESP32-C6(beta)"
+    IMAGE_CHIP_ID = 7
+
+    CHIP_DETECT_MAGIC_VALUE = [0x0DA1806F]
+
+    UART_DATE_REG_ADDR = 0x00000500
+
+    def get_chip_description(self):
+        chip_name = {
+            0: "ESP32-C6",
+        }.get(self.get_pkg_version(), "unknown ESP32-C6")
+        major_rev = self.get_major_chip_version()
+        minor_rev = self.get_minor_chip_version()
+        return f"{chip_name} (revision v{major_rev}.{minor_rev})"
+
+    def _post_connect(self):
+        pass
@@ -0,0 +1,65 @@
+# SPDX-FileCopyrightText: 2022 Fredrik Ahlberg, Angus Gratton,
+# Espressif Systems (Shanghai) CO LTD, other contributors as noted.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from .esp32c6 import ESP32C6ROM
+
+
+class ESP32H2ROM(ESP32C6ROM):
+    CHIP_NAME = "ESP32-H2"
+    IMAGE_CHIP_ID = 16
+
+    # Magic value for ESP32H2
+    CHIP_DETECT_MAGIC_VALUE = [0xD7B73E80]
+
+    FLASH_FREQUENCY = {
+        "48m": 0xF,
+        "24m": 0x0,
+        "16m": 0x1,
+        "12m": 0x2,
+    }
+
+    def get_pkg_version(self):
+        num_word = 3
+        block1_addr = self.EFUSE_BASE + 0x044
+        word3 = self.read_reg(block1_addr + (4 * num_word))
+        pkg_version = (word3 >> 21) & 0x0F
+        return pkg_version
+
+    def get_chip_description(self):
+        chip_name = {
+            0: "ESP32-H2",
+        }.get(self.get_pkg_version(), "unknown ESP32-H2")
+        major_rev = self.get_major_chip_version()
+        minor_rev = self.get_minor_chip_version()
+        return f"{chip_name} (revision v{major_rev}.{minor_rev})"
+
+    def get_chip_features(self):
+        return ["BLE"]
+
+    def get_crystal_freq(self):
+        # ESP32H2 XTAL is fixed to 32MHz
+        return 32
+
+
+class ESP32H2StubLoader(ESP32H2ROM):
+    """Access class for ESP32H2 stub loader, runs on top of ROM.
+
+    (Basically the same as ESP32StubLoader, but different base class.
+    Can possibly be made into a mixin.)
+    """
+
+    FLASH_WRITE_SIZE = 0x4000  # matches MAX_WRITE_BLOCK in stub_loader.c
+    STATUS_BYTES_LENGTH = 2  # same as ESP8266, different to ESP32 ROM
+    IS_STUB = True
+
+    def __init__(self, rom_loader):
+        self.secure_download_mode = rom_loader.secure_download_mode
+        self._port = rom_loader._port
+        self._trace_enabled = rom_loader._trace_enabled
+        self.cache = rom_loader.cache
+        self.flush_input()  # resets _slip_reader
+
+
+ESP32H2ROM.STUB_CLASS = ESP32H2StubLoader
@@ -0,0 +1,164 @@
+# SPDX-FileCopyrightText: 2014-2022 Fredrik Ahlberg, Angus Gratton,
+# Espressif Systems (Shanghai) CO LTD, other contributors as noted.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import struct
+
+from .esp32c3 import ESP32C3ROM
+from ..util import FatalError, NotImplementedInROMError
+
+
+class ESP32H2BETA1ROM(ESP32C3ROM):
+    CHIP_NAME = "ESP32-H2(beta1)"
+    IMAGE_CHIP_ID = 10
+
+    IROM_MAP_START = 0x42000000
+    IROM_MAP_END = 0x42800000
+    DROM_MAP_START = 0x3C000000
+    DROM_MAP_END = 0x3C800000
+
+    SPI_REG_BASE = 0x60002000
+    SPI_USR_OFFS = 0x18
+    SPI_USR1_OFFS = 0x1C
+    SPI_USR2_OFFS = 0x20
+    SPI_MOSI_DLEN_OFFS = 0x24
+    SPI_MISO_DLEN_OFFS = 0x28
+    SPI_W0_OFFS = 0x58
+
+    BOOTLOADER_FLASH_OFFSET = 0x0
+
+    CHIP_DETECT_MAGIC_VALUE = [0xCA26CC22]
+
+    UART_DATE_REG_ADDR = 0x60000000 + 0x7C
+
+    EFUSE_BASE = 0x6001A000
+    EFUSE_BLOCK1_ADDR = EFUSE_BASE + 0x044
+    MAC_EFUSE_REG = EFUSE_BASE + 0x044
+
+    EFUSE_RD_REG_BASE = EFUSE_BASE + 0x030  # BLOCK0 read base address
+
+    EFUSE_PURPOSE_KEY0_REG = EFUSE_BASE + 0x34
+    EFUSE_PURPOSE_KEY0_SHIFT = 24
+    EFUSE_PURPOSE_KEY1_REG = EFUSE_BASE + 0x34
+    EFUSE_PURPOSE_KEY1_SHIFT = 28
+    EFUSE_PURPOSE_KEY2_REG = EFUSE_BASE + 0x38
+    EFUSE_PURPOSE_KEY2_SHIFT = 0
+    EFUSE_PURPOSE_KEY3_REG = EFUSE_BASE + 0x38
+    EFUSE_PURPOSE_KEY3_SHIFT = 4
+    EFUSE_PURPOSE_KEY4_REG = EFUSE_BASE + 0x38
+    EFUSE_PURPOSE_KEY4_SHIFT = 8
+    EFUSE_PURPOSE_KEY5_REG = EFUSE_BASE + 0x38
+    EFUSE_PURPOSE_KEY5_SHIFT = 12
+
+    EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_REG = EFUSE_RD_REG_BASE
+    EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT = 1 << 20
+
+    EFUSE_SPI_BOOT_CRYPT_CNT_REG = EFUSE_BASE + 0x034
+    EFUSE_SPI_BOOT_CRYPT_CNT_MASK = 0x7 << 18
+
+    EFUSE_SECURE_BOOT_EN_REG = EFUSE_BASE + 0x038
+    EFUSE_SECURE_BOOT_EN_MASK = 1 << 20
+
+    PURPOSE_VAL_XTS_AES128_KEY = 4
+
+    SUPPORTS_ENCRYPTED_FLASH = True
+
+    FLASH_ENCRYPTED_WRITE_ALIGN = 16
+
+    MEMORY_MAP = []
+
+    FLASH_FREQUENCY = {
+        "48m": 0xF,
+        "24m": 0x0,
+        "16m": 0x1,
+        "12m": 0x2,
+    }
+
+    def get_pkg_version(self):
+        num_word = 3
+        return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 21) & 0x0F
+
+    def get_minor_chip_version(self):
+        hi_num_word = 5
+        hi = (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * hi_num_word)) >> 23) & 0x01
+        low_num_word = 3
+        low = (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * low_num_word)) >> 18) & 0x07
+        return (hi << 3) + low
+
+    def get_major_chip_version(self):
+        num_word = 5
+        return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 24) & 0x03
+
+    def get_chip_description(self):
+        chip_name = {
+            0: "ESP32-H2",
+        }.get(self.get_pkg_version(), "unknown ESP32-H2")
+        major_rev = self.get_major_chip_version()
+        minor_rev = self.get_minor_chip_version()
+        return f"{chip_name} (revision v{major_rev}.{minor_rev})"
+
+    def get_chip_features(self):
+        return ["BLE", "IEEE802.15.4"]
+
+    def get_crystal_freq(self):
+        return 32
+
+    def override_vddsdio(self, new_voltage):
+        raise NotImplementedInROMError(
+            "VDD_SDIO overrides are not supported for ESP32-H2"
+        )
+
+    def read_mac(self):
+        mac0 = self.read_reg(self.MAC_EFUSE_REG)
+        mac1 = self.read_reg(self.MAC_EFUSE_REG + 4)  # only bottom 16 bits are MAC
+        bitstring = struct.pack(">II", mac1, mac0)[2:]
+        return tuple(bitstring)
+
+    def get_flash_crypt_config(self):
+        return None  # doesn't exist on ESP32-H2
+
+    def get_key_block_purpose(self, key_block):
+        if key_block < 0 or key_block > 5:
+            raise FatalError("Valid key block numbers must be in range 0-5")
+
+        reg, shift = [
+            (self.EFUSE_PURPOSE_KEY0_REG, self.EFUSE_PURPOSE_KEY0_SHIFT),
+            (self.EFUSE_PURPOSE_KEY1_REG, self.EFUSE_PURPOSE_KEY1_SHIFT),
+            (self.EFUSE_PURPOSE_KEY2_REG, self.EFUSE_PURPOSE_KEY2_SHIFT),
+            (self.EFUSE_PURPOSE_KEY3_REG, self.EFUSE_PURPOSE_KEY3_SHIFT),
+            (self.EFUSE_PURPOSE_KEY4_REG, self.EFUSE_PURPOSE_KEY4_SHIFT),
+            (self.EFUSE_PURPOSE_KEY5_REG, self.EFUSE_PURPOSE_KEY5_SHIFT),
+        ][key_block]
+        return (self.read_reg(reg) >> shift) & 0xF
+
+    def is_flash_encryption_key_valid(self):
+        # Need to see an AES-128 key
+        purposes = [self.get_key_block_purpose(b) for b in range(6)]
+
+        return any(p == self.PURPOSE_VAL_XTS_AES128_KEY for p in purposes)
+
+    def _post_connect(self):
+        pass
+
+
+class ESP32H2BETA1StubLoader(ESP32H2BETA1ROM):
+    """Access class for ESP32H2BETA1 stub loader, runs on top of ROM.
+
+    (Basically the same as ESP32StubLoader, but different base class.
+    Can possibly be made into a mixin.)
+    """
+
+    FLASH_WRITE_SIZE = 0x4000  # matches MAX_WRITE_BLOCK in stub_loader.c
+    STATUS_BYTES_LENGTH = 2  # same as ESP8266, different to ESP32 ROM
+    IS_STUB = True
+
+    def __init__(self, rom_loader):
+        self.secure_download_mode = rom_loader.secure_download_mode
+        self._port = rom_loader._port
+        self._trace_enabled = rom_loader._trace_enabled
+        self.cache = rom_loader.cache
+        self.flush_input()  # resets _slip_reader
+
+
+ESP32H2BETA1ROM.STUB_CLASS = ESP32H2BETA1StubLoader
@@ -0,0 +1,43 @@
+# SPDX-FileCopyrightText: 2014-2022 Fredrik Ahlberg, Angus Gratton,
+# Espressif Systems (Shanghai) CO LTD, other contributors as noted.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from .esp32h2beta1 import ESP32H2BETA1ROM
+
+
+class ESP32H2BETA2ROM(ESP32H2BETA1ROM):
+    CHIP_NAME = "ESP32-H2(beta2)"
+    IMAGE_CHIP_ID = 14
+
+    CHIP_DETECT_MAGIC_VALUE = [0x6881B06F]
+
+    def get_chip_description(self):
+        chip_name = {
+            1: "ESP32-H2(beta2)",
+        }.get(self.get_pkg_version(), "unknown ESP32-H2")
+        major_rev = self.get_major_chip_version()
+        minor_rev = self.get_minor_chip_version()
+        return f"{chip_name} (revision v{major_rev}.{minor_rev})"
+
+
+class ESP32H2BETA2StubLoader(ESP32H2BETA2ROM):
+    """Access class for ESP32H2BETA2 stub loader, runs on top of ROM.
+
+    (Basically the same as ESP32StubLoader, but different base class.
+    Can possibly be made into a mixin.)
+    """
+
+    FLASH_WRITE_SIZE = 0x4000  # matches MAX_WRITE_BLOCK in stub_loader.c
+    STATUS_BYTES_LENGTH = 2  # same as ESP8266, different to ESP32 ROM
+    IS_STUB = True
+
+    def __init__(self, rom_loader):
+        self.secure_download_mode = rom_loader.secure_download_mode
+        self._port = rom_loader._port
+        self._trace_enabled = rom_loader._trace_enabled
+        self.cache = rom_loader.cache
+        self.flush_input()  # resets _slip_reader
+
+
+ESP32H2BETA2ROM.STUB_CLASS = ESP32H2BETA2StubLoader
@@ -0,0 +1,305 @@
+# SPDX-FileCopyrightText: 2014-2023 Fredrik Ahlberg, Angus Gratton,
+# Espressif Systems (Shanghai) CO LTD, other contributors as noted.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import os
+import struct
+
+from .esp32 import ESP32ROM
+from ..loader import ESPLoader
+from ..reset import HardReset
+from ..util import FatalError, NotImplementedInROMError
+
+
+class ESP32S2ROM(ESP32ROM):
+    CHIP_NAME = "ESP32-S2"
+    IMAGE_CHIP_ID = 2
+
+    FPGA_SLOW_BOOT = False
+
+    IROM_MAP_START = 0x40080000
+    IROM_MAP_END = 0x40B80000
+    DROM_MAP_START = 0x3F000000
+    DROM_MAP_END = 0x3F3F0000
+
+    CHIP_DETECT_MAGIC_VALUE = [0x000007C6]
+
+    SPI_REG_BASE = 0x3F402000
+    SPI_USR_OFFS = 0x18
+    SPI_USR1_OFFS = 0x1C
+    SPI_USR2_OFFS = 0x20
+    SPI_MOSI_DLEN_OFFS = 0x24
+    SPI_MISO_DLEN_OFFS = 0x28
+    SPI_W0_OFFS = 0x58
+
+    MAC_EFUSE_REG = 0x3F41A044  # ESP32-S2 has special block for MAC efuses
+
+    UART_CLKDIV_REG = 0x3F400014
+
+    SUPPORTS_ENCRYPTED_FLASH = True
+
+    FLASH_ENCRYPTED_WRITE_ALIGN = 16
+
+    # todo: use espefuse APIs to get this info
+    EFUSE_BASE = 0x3F41A000
+    EFUSE_RD_REG_BASE = EFUSE_BASE + 0x030  # BLOCK0 read base address
+    EFUSE_BLOCK1_ADDR = EFUSE_BASE + 0x044
+    EFUSE_BLOCK2_ADDR = EFUSE_BASE + 0x05C
+
+    EFUSE_PURPOSE_KEY0_REG = EFUSE_BASE + 0x34
+    EFUSE_PURPOSE_KEY0_SHIFT = 24
+    EFUSE_PURPOSE_KEY1_REG = EFUSE_BASE + 0x34
+    EFUSE_PURPOSE_KEY1_SHIFT = 28
+    EFUSE_PURPOSE_KEY2_REG = EFUSE_BASE + 0x38
+    EFUSE_PURPOSE_KEY2_SHIFT = 0
+    EFUSE_PURPOSE_KEY3_REG = EFUSE_BASE + 0x38
+    EFUSE_PURPOSE_KEY3_SHIFT = 4
+    EFUSE_PURPOSE_KEY4_REG = EFUSE_BASE + 0x38
+    EFUSE_PURPOSE_KEY4_SHIFT = 8
+    EFUSE_PURPOSE_KEY5_REG = EFUSE_BASE + 0x38
+    EFUSE_PURPOSE_KEY5_SHIFT = 12
+
+    EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_REG = EFUSE_RD_REG_BASE
+    EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT = 1 << 19
+
+    EFUSE_SPI_BOOT_CRYPT_CNT_REG = EFUSE_BASE + 0x034
+    EFUSE_SPI_BOOT_CRYPT_CNT_MASK = 0x7 << 18
+
+    EFUSE_SECURE_BOOT_EN_REG = EFUSE_BASE + 0x038
+    EFUSE_SECURE_BOOT_EN_MASK = 1 << 20
+
+    EFUSE_RD_REPEAT_DATA3_REG = EFUSE_BASE + 0x3C
+    EFUSE_RD_REPEAT_DATA3_REG_FLASH_TYPE_MASK = 1 << 9
+
+    PURPOSE_VAL_XTS_AES256_KEY_1 = 2
+    PURPOSE_VAL_XTS_AES256_KEY_2 = 3
+    PURPOSE_VAL_XTS_AES128_KEY = 4
+
+    UARTDEV_BUF_NO = 0x3FFFFD14  # Variable in ROM .bss which indicates the port in use
+    UARTDEV_BUF_NO_USB_OTG = 2  # Value of the above indicating that USB-OTG is in use
+
+    USB_RAM_BLOCK = 0x800  # Max block size USB-OTG is used
+
+    GPIO_STRAP_REG = 0x3F404038
+    GPIO_STRAP_SPI_BOOT_MASK = 0x8  # Not download mode
+    RTC_CNTL_OPTION1_REG = 0x3F408128
+    RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x1  # Is download mode forced over USB?
+
+    MEMORY_MAP = [
+        [0x00000000, 0x00010000, "PADDING"],
+        [0x3F000000, 0x3FF80000, "DROM"],
+        [0x3F500000, 0x3FF80000, "EXTRAM_DATA"],
+        [0x3FF9E000, 0x3FFA0000, "RTC_DRAM"],
+        [0x3FF9E000, 0x40000000, "BYTE_ACCESSIBLE"],
+        [0x3FF9E000, 0x40072000, "MEM_INTERNAL"],
+        [0x3FFB0000, 0x40000000, "DRAM"],
+        [0x40000000, 0x4001A100, "IROM_MASK"],
+        [0x40020000, 0x40070000, "IRAM"],
+        [0x40070000, 0x40072000, "RTC_IRAM"],
+        [0x40080000, 0x40800000, "IROM"],
+        [0x50000000, 0x50002000, "RTC_DATA"],
+    ]
+
+    def get_pkg_version(self):
+        num_word = 4
+        return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 0) & 0x0F
+
+    def get_minor_chip_version(self):
+        hi_num_word = 3
+        hi = (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * hi_num_word)) >> 20) & 0x01
+        low_num_word = 4
+        low = (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * low_num_word)) >> 4) & 0x07
+        return (hi << 3) + low
+
+    def get_major_chip_version(self):
+        num_word = 3
+        return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 18) & 0x03
+
+    def get_flash_version(self):
+        num_word = 3
+        return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 21) & 0x0F
+
+    def get_psram_version(self):
+        num_word = 3
+        return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 28) & 0x0F
+
+    def get_block2_version(self):
+        # BLK_VERSION_MINOR
+        num_word = 4
+        return (self.read_reg(self.EFUSE_BLOCK2_ADDR + (4 * num_word)) >> 4) & 0x07
+
+    def get_chip_description(self):
+        chip_name = {
+            0: "ESP32-S2",
+            1: "ESP32-S2FH2",
+            2: "ESP32-S2FH4",
+            102: "ESP32-S2FNR2",
+            100: "ESP32-S2R2",
+        }.get(
+            self.get_flash_version() + self.get_psram_version() * 100,
+            "unknown ESP32-S2",
+        )
+        major_rev = self.get_major_chip_version()
+        minor_rev = self.get_minor_chip_version()
+        return f"{chip_name} (revision v{major_rev}.{minor_rev})"
+
+    def get_chip_features(self):
+        features = ["WiFi"]
+
+        if self.secure_download_mode:
+            features += ["Secure Download Mode Enabled"]
+
+        flash_version = {
+            0: "No Embedded Flash",
+            1: "Embedded Flash 2MB",
+            2: "Embedded Flash 4MB",
+        }.get(self.get_flash_version(), "Unknown Embedded Flash")
+        features += [flash_version]
+
+        psram_version = {
+            0: "No Embedded PSRAM",
+            1: "Embedded PSRAM 2MB",
+            2: "Embedded PSRAM 4MB",
+        }.get(self.get_psram_version(), "Unknown Embedded PSRAM")
+        features += [psram_version]
+
+        block2_version = {
+            0: "No calibration in BLK2 of efuse",
+            1: "ADC and temperature sensor calibration in BLK2 of efuse V1",
+            2: "ADC and temperature sensor calibration in BLK2 of efuse V2",
+        }.get(self.get_block2_version(), "Unknown Calibration in BLK2")
+        features += [block2_version]
+
+        return features
+
+    def get_crystal_freq(self):
+        # ESP32-S2 XTAL is fixed to 40MHz
+        return 40
+
+    def override_vddsdio(self, new_voltage):
+        raise NotImplementedInROMError(
+            "VDD_SDIO overrides are not supported for ESP32-S2"
+        )
+
+    def read_mac(self):
+        mac0 = self.read_reg(self.MAC_EFUSE_REG)
+        mac1 = self.read_reg(self.MAC_EFUSE_REG + 4)  # only bottom 16 bits are MAC
+        bitstring = struct.pack(">II", mac1, mac0)[2:]
+        return tuple(bitstring)
+
+    def flash_type(self):
+        return (
+            1
+            if self.read_reg(self.EFUSE_RD_REPEAT_DATA3_REG)
+            & self.EFUSE_RD_REPEAT_DATA3_REG_FLASH_TYPE_MASK
+            else 0
+        )
+
+    def get_flash_crypt_config(self):
+        return None  # doesn't exist on ESP32-S2
+
+    def get_secure_boot_enabled(self):
+        return (
+            self.read_reg(self.EFUSE_SECURE_BOOT_EN_REG)
+            & self.EFUSE_SECURE_BOOT_EN_MASK
+        )
+
+    def get_key_block_purpose(self, key_block):
+        if key_block < 0 or key_block > 5:
+            raise FatalError("Valid key block numbers must be in range 0-5")
+
+        reg, shift = [
+            (self.EFUSE_PURPOSE_KEY0_REG, self.EFUSE_PURPOSE_KEY0_SHIFT),
+            (self.EFUSE_PURPOSE_KEY1_REG, self.EFUSE_PURPOSE_KEY1_SHIFT),
+            (self.EFUSE_PURPOSE_KEY2_REG, self.EFUSE_PURPOSE_KEY2_SHIFT),
+            (self.EFUSE_PURPOSE_KEY3_REG, self.EFUSE_PURPOSE_KEY3_SHIFT),
+            (self.EFUSE_PURPOSE_KEY4_REG, self.EFUSE_PURPOSE_KEY4_SHIFT),
+            (self.EFUSE_PURPOSE_KEY5_REG, self.EFUSE_PURPOSE_KEY5_SHIFT),
+        ][key_block]
+        return (self.read_reg(reg) >> shift) & 0xF
+
+    def is_flash_encryption_key_valid(self):
+        # Need to see either an AES-128 key or two AES-256 keys
+        purposes = [self.get_key_block_purpose(b) for b in range(6)]
+
+        if any(p == self.PURPOSE_VAL_XTS_AES128_KEY for p in purposes):
+            return True
+
+        return any(p == self.PURPOSE_VAL_XTS_AES256_KEY_1 for p in purposes) and any(
+            p == self.PURPOSE_VAL_XTS_AES256_KEY_2 for p in purposes
+        )
+
+    def uses_usb_otg(self):
+        """
+        Check the UARTDEV_BUF_NO register to see if USB-OTG console is being used
+        """
+        if self.secure_download_mode:
+            return False  # can't detect native USB in secure download mode
+        return self.get_uart_no() == self.UARTDEV_BUF_NO_USB_OTG
+
+    def _post_connect(self):
+        if self.uses_usb_otg():
+            self.ESP_RAM_BLOCK = self.USB_RAM_BLOCK
+
+    def _check_if_can_reset(self):
+        """
+        Check the strapping register to see if we can reset out of download mode.
+        """
+        if os.getenv("ESPTOOL_TESTING") is not None:
+            print("ESPTOOL_TESTING is set, ignoring strapping mode check")
+            # Esptool tests over USB-OTG run with GPIO0 strapped low,
+            # don't complain in this case.
+            return
+        strap_reg = self.read_reg(self.GPIO_STRAP_REG)
+        force_dl_reg = self.read_reg(self.RTC_CNTL_OPTION1_REG)
+        if (
+            strap_reg & self.GPIO_STRAP_SPI_BOOT_MASK == 0
+            and force_dl_reg & self.RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK == 0
+        ):
+            print(
+                "WARNING: {} chip was placed into download mode using GPIO0.\n"
+                "esptool.py can not exit the download mode over USB. "
+                "To run the app, reset the chip manually.\n"
+                "To suppress this note, set --after option to 'no_reset'.".format(
+                    self.get_chip_description()
+                )
+            )
+            raise SystemExit(1)
+
+    def hard_reset(self):
+        uses_usb_otg = self.uses_usb_otg()
+        if uses_usb_otg:
+            self._check_if_can_reset()
+
+        print("Hard resetting via RTS pin...")
+        HardReset(self._port, uses_usb_otg)()
+
+    def change_baud(self, baud):
+        ESPLoader.change_baud(self, baud)
+
+
+class ESP32S2StubLoader(ESP32S2ROM):
+    """Access class for ESP32-S2 stub loader, runs on top of ROM.
+
+    (Basically the same as ESP32StubLoader, but different base class.
+    Can possibly be made into a mixin.)
+    """
+
+    FLASH_WRITE_SIZE = 0x4000  # matches MAX_WRITE_BLOCK in stub_loader.c
+    STATUS_BYTES_LENGTH = 2  # same as ESP8266, different to ESP32 ROM
+    IS_STUB = True
+
+    def __init__(self, rom_loader):
+        self.secure_download_mode = rom_loader.secure_download_mode
+        self._port = rom_loader._port
+        self._trace_enabled = rom_loader._trace_enabled
+        self.cache = rom_loader.cache
+        self.flush_input()  # resets _slip_reader
+
+        if rom_loader.uses_usb_otg():
+            self.ESP_RAM_BLOCK = self.USB_RAM_BLOCK
+            self.FLASH_WRITE_SIZE = self.USB_RAM_BLOCK
+
+
+ESP32S2ROM.STUB_CLASS = ESP32S2StubLoader
@@ -0,0 +1,315 @@
+# SPDX-FileCopyrightText: 2014-2023 Fredrik Ahlberg, Angus Gratton,
+# Espressif Systems (Shanghai) CO LTD, other contributors as noted.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import os
+import struct
+
+from .esp32 import ESP32ROM
+from ..loader import ESPLoader
+from ..reset import HardReset
+from ..util import FatalError, NotImplementedInROMError
+
+
+class ESP32S3ROM(ESP32ROM):
+    CHIP_NAME = "ESP32-S3"
+
+    IMAGE_CHIP_ID = 9
+
+    CHIP_DETECT_MAGIC_VALUE = [0x9]
+
+    FPGA_SLOW_BOOT = False
+
+    IROM_MAP_START = 0x42000000
+    IROM_MAP_END = 0x44000000
+    DROM_MAP_START = 0x3C000000
+    DROM_MAP_END = 0x3E000000
+
+    UART_DATE_REG_ADDR = 0x60000080
+
+    SPI_REG_BASE = 0x60002000
+    SPI_USR_OFFS = 0x18
+    SPI_USR1_OFFS = 0x1C
+    SPI_USR2_OFFS = 0x20
+    SPI_MOSI_DLEN_OFFS = 0x24
+    SPI_MISO_DLEN_OFFS = 0x28
+    SPI_W0_OFFS = 0x58
+
+    BOOTLOADER_FLASH_OFFSET = 0x0
+
+    SUPPORTS_ENCRYPTED_FLASH = True
+
+    FLASH_ENCRYPTED_WRITE_ALIGN = 16
+
+    # todo: use espefuse APIs to get this info
+    EFUSE_BASE = 0x60007000  # BLOCK0 read base address
+    EFUSE_BLOCK1_ADDR = EFUSE_BASE + 0x44
+    EFUSE_BLOCK2_ADDR = EFUSE_BASE + 0x5C
+    MAC_EFUSE_REG = EFUSE_BASE + 0x044
+
+    EFUSE_RD_REG_BASE = EFUSE_BASE + 0x030  # BLOCK0 read base address
+
+    EFUSE_PURPOSE_KEY0_REG = EFUSE_BASE + 0x34
+    EFUSE_PURPOSE_KEY0_SHIFT = 24
+    EFUSE_PURPOSE_KEY1_REG = EFUSE_BASE + 0x34
+    EFUSE_PURPOSE_KEY1_SHIFT = 28
+    EFUSE_PURPOSE_KEY2_REG = EFUSE_BASE + 0x38
+    EFUSE_PURPOSE_KEY2_SHIFT = 0
+    EFUSE_PURPOSE_KEY3_REG = EFUSE_BASE + 0x38
+    EFUSE_PURPOSE_KEY3_SHIFT = 4
+    EFUSE_PURPOSE_KEY4_REG = EFUSE_BASE + 0x38
+    EFUSE_PURPOSE_KEY4_SHIFT = 8
+    EFUSE_PURPOSE_KEY5_REG = EFUSE_BASE + 0x38
+    EFUSE_PURPOSE_KEY5_SHIFT = 12
+
+    EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_REG = EFUSE_RD_REG_BASE
+    EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT = 1 << 20
+
+    EFUSE_SPI_BOOT_CRYPT_CNT_REG = EFUSE_BASE + 0x034
+    EFUSE_SPI_BOOT_CRYPT_CNT_MASK = 0x7 << 18
+
+    EFUSE_SECURE_BOOT_EN_REG = EFUSE_BASE + 0x038
+    EFUSE_SECURE_BOOT_EN_MASK = 1 << 20
+
+    EFUSE_RD_REPEAT_DATA3_REG = EFUSE_BASE + 0x3C
+    EFUSE_RD_REPEAT_DATA3_REG_FLASH_TYPE_MASK = 1 << 9
+
+    PURPOSE_VAL_XTS_AES256_KEY_1 = 2
+    PURPOSE_VAL_XTS_AES256_KEY_2 = 3
+    PURPOSE_VAL_XTS_AES128_KEY = 4
+
+    UARTDEV_BUF_NO = 0x3FCEF14C  # Variable in ROM .bss which indicates the port in use
+    UARTDEV_BUF_NO_USB_OTG = 3  # The above var when USB-OTG is used
+    UARTDEV_BUF_NO_USB_JTAG_SERIAL = 4  # The above var when USB-JTAG/Serial is used
+
+    RTC_CNTL_WDT_WKEY = 0x50D83AA1
+    RTCCNTL_BASE_REG = 0x60008000
+    RTC_CNTL_WDTCONFIG0_REG = RTCCNTL_BASE_REG + 0x0090
+    RTC_CNTL_WDTWPROTECT_REG = RTCCNTL_BASE_REG + 0x00B0
+
+    USB_RAM_BLOCK = 0x800  # Max block size USB-OTG is used
+
+    GPIO_STRAP_REG = 0x60004038
+    GPIO_STRAP_SPI_BOOT_MASK = 0x8  # Not download mode
+    RTC_CNTL_OPTION1_REG = 0x6000812C
+    RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK = 0x1  # Is download mode forced over USB?
+
+    UART_CLKDIV_REG = 0x60000014
+
+    MEMORY_MAP = [
+        [0x00000000, 0x00010000, "PADDING"],
+        [0x3C000000, 0x3D000000, "DROM"],
+        [0x3D000000, 0x3E000000, "EXTRAM_DATA"],
+        [0x600FE000, 0x60100000, "RTC_DRAM"],
+        [0x3FC88000, 0x3FD00000, "BYTE_ACCESSIBLE"],
+        [0x3FC88000, 0x403E2000, "MEM_INTERNAL"],
+        [0x3FC88000, 0x3FD00000, "DRAM"],
+        [0x40000000, 0x4001A100, "IROM_MASK"],
+        [0x40370000, 0x403E0000, "IRAM"],
+        [0x600FE000, 0x60100000, "RTC_IRAM"],
+        [0x42000000, 0x42800000, "IROM"],
+        [0x50000000, 0x50002000, "RTC_DATA"],
+    ]
+
+    def get_pkg_version(self):
+        num_word = 3
+        return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 21) & 0x07
+
+    def is_eco0(self, minor_raw):
+        # Workaround: The major version field was allocated to other purposes
+        # when block version is v1.1.
+        # Luckily only chip v0.0 have this kind of block version and efuse usage.
+        return (
+            (minor_raw & 0x7) == 0
+            and self.get_blk_version_major() == 1
+            and self.get_blk_version_minor() == 1
+        )
+
+    def get_minor_chip_version(self):
+        minor_raw = self.get_raw_minor_chip_version()
+        if self.is_eco0(minor_raw):
+            return 0
+        return minor_raw
+
+    def get_raw_minor_chip_version(self):
+        hi_num_word = 5
+        hi = (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * hi_num_word)) >> 23) & 0x01
+        low_num_word = 3
+        low = (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * low_num_word)) >> 18) & 0x07
+        return (hi << 3) + low
+
+    def get_blk_version_major(self):
+        num_word = 4
+        return (self.read_reg(self.EFUSE_BLOCK2_ADDR + (4 * num_word)) >> 0) & 0x03
+
+    def get_blk_version_minor(self):
+        num_word = 3
+        return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 24) & 0x07
+
+    def get_major_chip_version(self):
+        minor_raw = self.get_raw_minor_chip_version()
+        if self.is_eco0(minor_raw):
+            return 0
+        return self.get_raw_major_chip_version()
+
+    def get_raw_major_chip_version(self):
+        num_word = 5
+        return (self.read_reg(self.EFUSE_BLOCK1_ADDR + (4 * num_word)) >> 24) & 0x03
+
+    def get_chip_description(self):
+        major_rev = self.get_major_chip_version()
+        minor_rev = self.get_minor_chip_version()
+        return f"{self.CHIP_NAME} (revision v{major_rev}.{minor_rev})"
+
+    def get_chip_features(self):
+        return ["WiFi", "BLE"]
+
+    def get_crystal_freq(self):
+        # ESP32S3 XTAL is fixed to 40MHz
+        return 40
+
+    def get_flash_crypt_config(self):
+        return None  # doesn't exist on ESP32-S3
+
+    def get_key_block_purpose(self, key_block):
+        if key_block < 0 or key_block > 5:
+            raise FatalError("Valid key block numbers must be in range 0-5")
+
+        reg, shift = [
+            (self.EFUSE_PURPOSE_KEY0_REG, self.EFUSE_PURPOSE_KEY0_SHIFT),
+            (self.EFUSE_PURPOSE_KEY1_REG, self.EFUSE_PURPOSE_KEY1_SHIFT),
+            (self.EFUSE_PURPOSE_KEY2_REG, self.EFUSE_PURPOSE_KEY2_SHIFT),
+            (self.EFUSE_PURPOSE_KEY3_REG, self.EFUSE_PURPOSE_KEY3_SHIFT),
+            (self.EFUSE_PURPOSE_KEY4_REG, self.EFUSE_PURPOSE_KEY4_SHIFT),
+            (self.EFUSE_PURPOSE_KEY5_REG, self.EFUSE_PURPOSE_KEY5_SHIFT),
+        ][key_block]
+        return (self.read_reg(reg) >> shift) & 0xF
+
+    def is_flash_encryption_key_valid(self):
+        # Need to see either an AES-128 key or two AES-256 keys
+        purposes = [self.get_key_block_purpose(b) for b in range(6)]
+
+        if any(p == self.PURPOSE_VAL_XTS_AES128_KEY for p in purposes):
+            return True
+
+        return any(p == self.PURPOSE_VAL_XTS_AES256_KEY_1 for p in purposes) and any(
+            p == self.PURPOSE_VAL_XTS_AES256_KEY_2 for p in purposes
+        )
+
+    def get_secure_boot_enabled(self):
+        return (
+            self.read_reg(self.EFUSE_SECURE_BOOT_EN_REG)
+            & self.EFUSE_SECURE_BOOT_EN_MASK
+        )
+
+    def override_vddsdio(self, new_voltage):
+        raise NotImplementedInROMError(
+            "VDD_SDIO overrides are not supported for ESP32-S3"
+        )
+
+    def read_mac(self):
+        mac0 = self.read_reg(self.MAC_EFUSE_REG)
+        mac1 = self.read_reg(self.MAC_EFUSE_REG + 4)  # only bottom 16 bits are MAC
+        bitstring = struct.pack(">II", mac1, mac0)[2:]
+        return tuple(bitstring)
+
+    def flash_type(self):
+        return (
+            1
+            if self.read_reg(self.EFUSE_RD_REPEAT_DATA3_REG)
+            & self.EFUSE_RD_REPEAT_DATA3_REG_FLASH_TYPE_MASK
+            else 0
+        )
+
+    def uses_usb_otg(self):
+        """
+        Check the UARTDEV_BUF_NO register to see if USB-OTG console is being used
+        """
+        if self.secure_download_mode:
+            return False  # can't detect native USB in secure download mode
+        return self.get_uart_no() == self.UARTDEV_BUF_NO_USB_OTG
+
+    def uses_usb_jtag_serial(self):
+        """
+        Check the UARTDEV_BUF_NO register to see if USB-JTAG/Serial is being used
+        """
+        if self.secure_download_mode:
+            return False  # can't detect USB-JTAG/Serial in secure download mode
+        return self.get_uart_no() == self.UARTDEV_BUF_NO_USB_JTAG_SERIAL
+
+    def disable_rtc_watchdog(self):
+        # When USB-JTAG/Serial is used, the RTC watchdog is not reset
+        # and can then reset the board during flashing. Disable it.
+        if self.uses_usb_jtag_serial():
+            self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, self.RTC_CNTL_WDT_WKEY)
+            self.write_reg(self.RTC_CNTL_WDTCONFIG0_REG, 0)
+            self.write_reg(self.RTC_CNTL_WDTWPROTECT_REG, 0)
+
+    def _post_connect(self):
+        if self.uses_usb_otg():
+            self.ESP_RAM_BLOCK = self.USB_RAM_BLOCK
+        if not self.sync_stub_detected:  # Don't run if stub is reused
+            self.disable_rtc_watchdog()
+
+    def _check_if_can_reset(self):
+        """
+        Check the strapping register to see if we can reset out of download mode.
+        """
+        if os.getenv("ESPTOOL_TESTING") is not None:
+            print("ESPTOOL_TESTING is set, ignoring strapping mode check")
+            # Esptool tests over USB-OTG run with GPIO0 strapped low,
+            # don't complain in this case.
+            return
+        strap_reg = self.read_reg(self.GPIO_STRAP_REG)
+        force_dl_reg = self.read_reg(self.RTC_CNTL_OPTION1_REG)
+        if (
+            strap_reg & self.GPIO_STRAP_SPI_BOOT_MASK == 0
+            and force_dl_reg & self.RTC_CNTL_FORCE_DOWNLOAD_BOOT_MASK == 0
+        ):
+            print(
+                "WARNING: {} chip was placed into download mode using GPIO0.\n"
+                "esptool.py can not exit the download mode over USB. "
+                "To run the app, reset the chip manually.\n"
+                "To suppress this note, set --after option to 'no_reset'.".format(
+                    self.get_chip_description()
+                )
+            )
+            raise SystemExit(1)
+
+    def hard_reset(self):
+        uses_usb_otg = self.uses_usb_otg()
+        if uses_usb_otg:
+            self._check_if_can_reset()
+
+        print("Hard resetting via RTS pin...")
+        HardReset(self._port, uses_usb_otg)()
+
+    def change_baud(self, baud):
+        ESPLoader.change_baud(self, baud)
+
+
+class ESP32S3StubLoader(ESP32S3ROM):
+    """Access class for ESP32S3 stub loader, runs on top of ROM.
+
+    (Basically the same as ESP32StubLoader, but different base class.
+    Can possibly be made into a mixin.)
+    """
+
+    FLASH_WRITE_SIZE = 0x4000  # matches MAX_WRITE_BLOCK in stub_loader.c
+    STATUS_BYTES_LENGTH = 2  # same as ESP8266, different to ESP32 ROM
+    IS_STUB = True
+
+    def __init__(self, rom_loader):
+        self.secure_download_mode = rom_loader.secure_download_mode
+        self._port = rom_loader._port
+        self._trace_enabled = rom_loader._trace_enabled
+        self.cache = rom_loader.cache
+        self.flush_input()  # resets _slip_reader
+
+        if rom_loader.uses_usb_otg():
+            self.ESP_RAM_BLOCK = self.USB_RAM_BLOCK
+            self.FLASH_WRITE_SIZE = self.USB_RAM_BLOCK
+
+
+ESP32S3ROM.STUB_CLASS = ESP32S3StubLoader
@@ -0,0 +1,42 @@
+# SPDX-FileCopyrightText: 2014-2022 Fredrik Ahlberg, Angus Gratton,
+# Espressif Systems (Shanghai) CO LTD, other contributors as noted.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from .esp32s3 import ESP32S3ROM
+
+
+class ESP32S3BETA2ROM(ESP32S3ROM):
+    CHIP_NAME = "ESP32-S3(beta2)"
+    IMAGE_CHIP_ID = 4
+
+    CHIP_DETECT_MAGIC_VALUE = [0xEB004136]
+
+    EFUSE_BASE = 0x6001A000  # BLOCK0 read base address
+
+    def get_chip_description(self):
+        major_rev = self.get_major_chip_version()
+        minor_rev = self.get_minor_chip_version()
+        return f"{self.CHIP_NAME} (revision v{major_rev}.{minor_rev})"
+
+
+class ESP32S3BETA2StubLoader(ESP32S3BETA2ROM):
+    """Access class for ESP32S3 stub loader, runs on top of ROM.
+
+    (Basically the same as ESP32StubLoader, but different base class.
+    Can possibly be made into a mixin.)
+    """
+
+    FLASH_WRITE_SIZE = 0x4000  # matches MAX_WRITE_BLOCK in stub_loader.c
+    STATUS_BYTES_LENGTH = 2  # same as ESP8266, different to ESP32 ROM
+    IS_STUB = True
+
+    def __init__(self, rom_loader):
+        self.secure_download_mode = rom_loader.secure_download_mode
+        self._port = rom_loader._port
+        self._trace_enabled = rom_loader._trace_enabled
+        self.cache = rom_loader.cache
+        self.flush_input()  # resets _slip_reader
+
+
+ESP32S3BETA2ROM.STUB_CLASS = ESP32S3BETA2StubLoader
@@ -0,0 +1,191 @@
+# SPDX-FileCopyrightText: 2014-2022 Fredrik Ahlberg, Angus Gratton,
+# Espressif Systems (Shanghai) CO LTD, other contributors as noted.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+from ..loader import ESPLoader
+from ..util import FatalError, NotImplementedInROMError
+
+
+class ESP8266ROM(ESPLoader):
+    """Access class for ESP8266 ROM bootloader"""
+
+    CHIP_NAME = "ESP8266"
+    IS_STUB = False
+
+    CHIP_DETECT_MAGIC_VALUE = [0xFFF0C101]
+
+    # OTP ROM addresses
+    ESP_OTP_MAC0 = 0x3FF00050
+    ESP_OTP_MAC1 = 0x3FF00054
+    ESP_OTP_MAC3 = 0x3FF0005C
+
+    SPI_REG_BASE = 0x60000200
+    SPI_USR_OFFS = 0x1C
+    SPI_USR1_OFFS = 0x20
+    SPI_USR2_OFFS = 0x24
+    SPI_MOSI_DLEN_OFFS = None
+    SPI_MISO_DLEN_OFFS = None
+    SPI_W0_OFFS = 0x40
+
+    UART_CLKDIV_REG = 0x60000014
+
+    XTAL_CLK_DIVIDER = 2
+
+    FLASH_SIZES = {
+        "512KB": 0x00,
+        "256KB": 0x10,
+        "1MB": 0x20,
+        "2MB": 0x30,
+        "4MB": 0x40,
+        "2MB-c1": 0x50,
+        "4MB-c1": 0x60,
+        "8MB": 0x80,
+        "16MB": 0x90,
+    }
+
+    FLASH_FREQUENCY = {
+        "80m": 0xF,
+        "40m": 0x0,
+        "26m": 0x1,
+        "20m": 0x2,
+    }
+
+    BOOTLOADER_FLASH_OFFSET = 0
+
+    MEMORY_MAP = [
+        [0x3FF00000, 0x3FF00010, "DPORT"],
+        [0x3FFE8000, 0x40000000, "DRAM"],
+        [0x40100000, 0x40108000, "IRAM"],
+        [0x40201010, 0x402E1010, "IROM"],
+    ]
+
+    def get_efuses(self):
+        # Return the 128 bits of ESP8266 efuse as a single Python integer
+        result = self.read_reg(0x3FF0005C) << 96
+        result |= self.read_reg(0x3FF00058) << 64
+        result |= self.read_reg(0x3FF00054) << 32
+        result |= self.read_reg(0x3FF00050)
+        return result
+
+    def _get_flash_size(self, efuses):
+        # rX_Y = EFUSE_DATA_OUTX[Y]
+        r0_4 = (efuses & (1 << 4)) != 0
+        r3_25 = (efuses & (1 << 121)) != 0
+        r3_26 = (efuses & (1 << 122)) != 0
+        r3_27 = (efuses & (1 << 123)) != 0
+
+        if r0_4 and not r3_25:
+            if not r3_27 and not r3_26:
+                return 1
+            elif not r3_27 and r3_26:
+                return 2
+        if not r0_4 and r3_25:
+            if not r3_27 and not r3_26:
+                return 2
+            elif not r3_27 and r3_26:
+                return 4
+        return -1
+
+    def get_chip_description(self):
+        efuses = self.get_efuses()
+        is_8285 = (
+            efuses & ((1 << 4) | 1 << 80)
+        ) != 0  # One or the other efuse bit is set for ESP8285
+        if is_8285:
+            flash_size = self._get_flash_size(efuses)
+            max_temp = (
+                efuses & (1 << 5)
+            ) != 0  # This efuse bit identifies the max flash temperature
+            chip_name = {
+                1: "ESP8285H08" if max_temp else "ESP8285N08",
+                2: "ESP8285H16" if max_temp else "ESP8285N16",
+            }.get(flash_size, "ESP8285")
+            return chip_name
+        return "ESP8266EX"
+
+    def get_chip_features(self):
+        features = ["WiFi"]
+        if "ESP8285" in self.get_chip_description():
+            features += ["Embedded Flash"]
+        return features
+
+    def flash_spi_attach(self, hspi_arg):
+        if self.IS_STUB:
+            super(ESP8266ROM, self).flash_spi_attach(hspi_arg)
+        else:
+            # ESP8266 ROM has no flash_spi_attach command in serial protocol,
+            # but flash_begin will do it
+            self.flash_begin(0, 0)
+
+    def flash_set_parameters(self, size):
+        # not implemented in ROM, but OK to silently skip for ROM
+        if self.IS_STUB:
+            super(ESP8266ROM, self).flash_set_parameters(size)
+
+    def chip_id(self):
+        """
+        Read Chip ID from efuse - the equivalent of the SDK system_get_chip_id() func
+        """
+        id0 = self.read_reg(self.ESP_OTP_MAC0)
+        id1 = self.read_reg(self.ESP_OTP_MAC1)
+        return (id0 >> 24) | ((id1 & 0xFFFFFF) << 8)
+
+    def read_mac(self):
+        """Read MAC from OTP ROM"""
+        mac0 = self.read_reg(self.ESP_OTP_MAC0)
+        mac1 = self.read_reg(self.ESP_OTP_MAC1)
+        mac3 = self.read_reg(self.ESP_OTP_MAC3)
+        if mac3 != 0:
+            oui = ((mac3 >> 16) & 0xFF, (mac3 >> 8) & 0xFF, mac3 & 0xFF)
+        elif ((mac1 >> 16) & 0xFF) == 0:
+            oui = (0x18, 0xFE, 0x34)
+        elif ((mac1 >> 16) & 0xFF) == 1:
+            oui = (0xAC, 0xD0, 0x74)
+        else:
+            raise FatalError("Unknown OUI")
+        return oui + ((mac1 >> 8) & 0xFF, mac1 & 0xFF, (mac0 >> 24) & 0xFF)
+
+    def get_erase_size(self, offset, size):
+        """Calculate an erase size given a specific size in bytes.
+
+        Provides a workaround for the bootloader erase bug."""
+
+        sectors_per_block = 16
+        sector_size = self.FLASH_SECTOR_SIZE
+        num_sectors = (size + sector_size - 1) // sector_size
+        start_sector = offset // sector_size
+
+        head_sectors = sectors_per_block - (start_sector % sectors_per_block)
+        if num_sectors < head_sectors:
+            head_sectors = num_sectors
+
+        if num_sectors < 2 * head_sectors:
+            return (num_sectors + 1) // 2 * sector_size
+        else:
+            return (num_sectors - head_sectors) * sector_size
+
+    def override_vddsdio(self, new_voltage):
+        raise NotImplementedInROMError(
+            "Overriding VDDSDIO setting only applies to ESP32"
+        )
+
+
+class ESP8266StubLoader(ESP8266ROM):
+    """Access class for ESP8266 stub loader, runs on top of ROM."""
+
+    FLASH_WRITE_SIZE = 0x4000  # matches MAX_WRITE_BLOCK in stub_loader.c
+    IS_STUB = True
+
+    def __init__(self, rom_loader):
+        self.secure_download_mode = rom_loader.secure_download_mode
+        self._port = rom_loader._port
+        self._trace_enabled = rom_loader._trace_enabled
+        self.cache = rom_loader.cache
+        self.flush_input()  # resets _slip_reader
+
+    def get_erase_size(self, offset, size):
+        return size  # stub doesn't have same size bug as ROM loader
+
+
+ESP8266ROM.STUB_CLASS = ESP8266StubLoader
@@ -0,0 +1,7 @@
+{
+    "entry": 1074521560,
+    "text": "CAD0PxwA9D8AAPQ/AMD8PxAA9D82QQAh+v/AIAA4AkH5/8AgACgEICB0nOIGBQAAAEH1/4H2/8AgAKgEiAigoHTgCAALImYC54b0/yHx/8AgADkCHfAAAKDr/T8Ya/0/hIAAAEBAAABYq/0/pOv9PzZBALH5/yCgdBARIKXHAJYaBoH2/5KhAZCZEZqYwCAAuAmR8/+goHSaiMAgAJIYAJCQ9BvJwMD0wCAAwlgAmpvAIACiSQDAIACSGACB6v+QkPSAgPSHmUeB5f+SoQGQmRGamMAgAMgJoeX/seP/h5wXxgEAfOiHGt7GCADAIACJCsAgALkJRgIAwCAAuQrAIACJCZHX/5qIDAnAIACSWAAd8AAA+CD0P/gw9D82QQCR/f/AIACICYCAJFZI/5H6/8AgAIgJgIAkVkj/HfAAAAAQIPQ/ACD0PwAAAAg2QQAQESCl/P8h+v8MCMAgAIJiAJH6/4H4/8AgAJJoAMAgAJgIVnn/wCAAiAJ88oAiMCAgBB3wAAAAAEA2QQAQESDl+/8Wav+B7P+R+//AIACSaADAIACYCFZ5/x3wAAAMwPw/////AAQg9D82QQAh/P84QhaDBhARIGX4/xb6BQz4DAQ3qA2YIoCZEIKgAZBIg0BAdBARICX6/xARICXz/4giDBtAmBGQqwHMFICrAbHt/7CZELHs/8AgAJJrAJHO/8AgAKJpAMAgAKgJVnr/HAkMGkCag5AzwJqIOUKJIh3wAAAskgBANkEAoqDAgf3/4AgAHfAAADZBAIKgwK0Ch5IRoqDbgff/4AgAoqDcRgQAAAAAgqDbh5IIgfL/4AgAoqDdgfD/4AgAHfA2QQA6MsYCAACiAgAbIhARIKX7/zeS8R3wAAAAfNoFQNguBkCc2gVAHNsFQDYhIaLREIH6/+AIAEYLAAAADBRARBFAQ2PNBL0BrQKB9f/gCACgoHT8Ws0EELEgotEQgfH/4AgASiJAM8BWA/0iogsQIrAgoiCy0RCB7P/gCACtAhwLEBEgpff/LQOGAAAioGMd8AAA/GcAQNCSAEAIaABANkEhYqEHwGYRGmZZBiwKYtEQDAVSZhqB9//gCAAMGECIEUe4AkZFAK0GgdT/4AgAhjQAAJKkHVBzwOCZERqZQHdjiQnNB70BIKIggc3/4AgAkqQd4JkRGpmgoHSICYyqDAiCZhZ9CIYWAAAAkqQd4JkREJmAgmkAEBEgJer/vQetARARIKXt/xARICXp/80HELEgYKYggbv/4AgAkqQd4JkRGpmICXAigHBVgDe1sJKhB8CZERqZmAmAdcCXtwJG3P+G5v8MCIJGbKKkGxCqoIHK/+AIAFYK/7KiC6IGbBC7sBARIKWPAPfqEvZHD7KiDRC7sHq7oksAG3eG8f9867eawWZHCIImGje4Aoe1nCKiCxAisGC2IK0CgZv/4AgAEBEgpd//rQIcCxARICXj/xARIKXe/ywKgbH/4AgAHfAIIPQ/cOL6P0gkBkDwIgZANmEAEBEg5cr/EKEggfv/4AgAPQoMEvwqiAGSogCQiBCJARARIKXP/5Hy/6CiAcAgAIIpAKCIIMAgAIJpALIhAKHt/4Hu/+AIAKAjgx3wAAD/DwAANkEAgTv/DBmSSAAwnEGZKJH7/zkYKTgwMLSaIiozMDxBDAIpWDlIEBEgJfj/LQqMGiKgxR3wAABQLQZANkEAQSz/WDRQM2MWYwRYFFpTUFxBRgEAEBEgZcr/iESmGASIJIel7xARIKXC/xZq/6gUzQO9AoHx/+AIAKCgdIxKUqDEUmQFWBQ6VVkUWDQwVcBZNB3wAADA/D9PSEFJqOv9P3DgC0AU4AtADAD0PzhA9D///wAAjIAAABBAAACs6/0/vOv9PwTA/D8IwPw/BOz9PxQA9D/w//8AqOv9Pxjr/D8kwPw/fGgAQOxnAEBYhgBAbCoGQDgyBkAULAZAzCwGQEwsBkA0hQBAzJAAQHguBkAw7wVAWJIAQEyCAEA2wQAh3v8MCiJhCEKgAIHu/+AIACHZ/zHa/8YAAEkCSyI3MvgQESBlw/8MS6LBIBARIOXG/yKhARARICXC/1GR/pAiESolMc//sc//wCAAWQIheP4MDAxaMmIAgdz/4AgAMcr/QqEBwCAAKAMsCkAiIMAgACkDgTH/4AgAgdX/4AgAIcP/wCAAKALMuhzDMCIQIsL4DBMgo4MMC4HO/+AIAPG8/wwdwqABDBvioQBA3REAzBGAuwGioACBx//gCAAhtv8MBCpVIcP+ctIrwCAAKAUWcv/AIAA4BQwSwCAASQUiQRAiAwEMKCJBEYJRCUlRJpIHHDiHEh4GCAAiAwOCAwKAIhGAIiBmQhEoI8AgACgCKVFGAQAAHCIiUQkQESCls/8Mi6LBEBARIGW3/4IDAyIDAoCIESCIICGY/yAg9IeyHKKgwBARICWy/6Kg7hARIKWx/xARICWw/4bb/wAAIgMBHDknOTT2IhjG1AAAACLCLyAgdPZCcJGJ/5AioCgCoAIAIsL+ICB0HBknuQLGywCRhP+QIqAoAqACAJLCMJCQdLZZyQbGACxKbQQioMCnGAIGxABJUQxyrQQQESDlqv+tBBARIGWq/xARIOWo/xARIKWo/wyLosEQIsL/EBEg5av/ViL9RikADBJWyCyCYQ+Bev/gCACI8aAog8auACaIBAwSxqwAmCNoM2CJIICAtFbY/pnBEBEgZcf/mMFqKZwqBvf/AACgrEGBbf/gCABW6vxi1vBgosDMJgaBAACgkPRWGf6GBACgoPWZwYFl/+AIAJjBVpr6kGbADBkAmRFgosBnOeEGBAAAAKCsQYFc/+AIAFaq+GLW8GCiwFam/sZvAABtBCKgwCaIAoaNAG0EDALGiwAAACa484ZhAAwSJrgCBoUAuDOoIxARIOWh/6AkgwaBAAwcZrhTiEMgrBFtBCKgwoe6AoZ+ALhTqCPJ4RARIOXA/8YLAAwcZrgviEMgrBFtBCKgwoe6AoZ1ACgzuFOoIyBogsnhEBEgZb7/ITT+SWIi0itpIsjhoMSDLQyGaQChL/5tBLIKACKgxhY7GpgjgsjwIqDAh5kBKFoMCaKg70YCAJqzsgsYG5mwqjCHKfKCAwWSAwSAiBGQiCCSAwZtBACZEYCZIIIDB4CIAZCIIICqwIKgwaAok0ZVAIEY/m0EoggAIqDGFnoUqDgioMhW+hMoWKJIAMZNAByKbQQMEqcYAsZKAPhz6GPYU8hDuDOoI4EM/+AIAG0KoCSDRkQAAAwSJkgCRj8AqCO9BIEE/+AIAAYeAICwNG0EIqDAVgsPgGRBi8N8/UYOAKg8ucHJ4dnRgQD/4AgAyOG4wSgsmByoDNIhDZCSECYCDsAgAOIqACAtMOAiECCZIMAgAJkKG7vCzBBnO8LGm/9mSAJGmv9tBCKgwAYmAAwSJrgCRiEAIdz+mFOII5kCIdv+iQItBIYcAGHX/gwb2AaCyPCtBC0EgCuT0KuDIKoQbQQioMZW6gXB0f4ioMnoDIc+U4DwFCKgwFavBC0KRgIAKqOoaksiqQmtCyD+wCqdhzLtFprfIcT++QyZAsZ7/wwSZogWIcH+iAIWKACCoMhJAiG9/kkCDBKAJINtBEYBAABtBCKg/yCgdBARIOV5/2CgdBARIGV5/xARIOV3/1aiviIDARwoJzge9jICBvf+IsL9ICB0DPgnuAKG8/6BrP6AIqAoAqACAIKg0ocSUoKg1IcSegbt/gAAAIgzoqJxwKoRaCOJ8YGw/uAIACGh/pGi/sAgACgCiPEgNDXAIhGQIhAgIyCAIoKtBGCywoGn/uAIAKKj6IGk/uAIAAbb/gAA2FPIQ7gzqCMQESAlff9G1v4AsgMDIgMCgLsRILsgssvwosMYEBEgZZn/Rs/+ACIDA4IDAmGP/YAiEZg2gCIgIsLwkCJjFiKymBaakpCcQUYCAJnBEBEgZWL/mMGoRqYaBKgmp6nrEBEgpVr/Fmr/qBbNArLDGIGG/uAIAIw6MqDEOVY4FiozORY4NiAjwCk2xrX+ggMCIsMYMgMDDByAMxGAMyAyw/AGIwCBbP6RHf3oCDlx4JnAmWGYJwwal7MBDDqJ8anR6cEQESAlW/+o0ZFj/ujBqQGhYv7dCb0CwsEc8sEYmcGBa/7gCAC4J80KqHGI8aC7wLknoDPAuAiqIqhhmMGqu90EDBq5CMDag5C7wNDgdMx90tuA0K6TFmoBrQmJ8ZnByeEQESAlif+I8ZjByOGSaABhTv2INoyjwJ8xwJnA1ikAVvj11qwAMUn9IqDHKVNGAACMPJwIxoL+FoigYUT9IqDIKVZGf/4AMUH9IqDJKVNGfP4oI1bCnq0EgUX+4AgAoqJxwKoRgT7+4AgAgUL+4AgAxnP+AAAoMxaCnK0EgTz+4AgAoqPogTb+4AgA4AIARmz+HfAAAAA2QQCdAoKgwCgDh5kPzDIMEoYHAAwCKQN84oYPACYSByYiGIYDAAAAgqDbgCkjh5kqDCIpA3zyRggAAAAioNwnmQoMEikDLQgGBAAAAIKg3Xzyh5kGDBIpAyKg2x3wAAA=",
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+    "data_start": 1073605544
+}
@@ -0,0 +1,7 @@
+{
+    "entry": 1077413304,
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