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error with XIAO ESP32S3 & Wio-SX1262 Kit for Meshtastic & LoRa #2

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opened 2026-10-05 06:05:45 +02:00 by adam · 13 comments
adam commented 2026-10-05 06:05:45 +02:00
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esptool --chip esp32s3 -p /dev/cu.usbmodem1CDBD4A894401 write-flash 0x0 ./lunar/lunarcore-esp32s3.bin
esptool v5.1.0
Serial port /dev/cu.usbmodem1CDBD4A894401:
Connecting.............

A serial exception error occurred: Could not configure port: (6, 'Device not configured')
Note: This error originates from pySerial. It is likely not a problem with esptool, but with the hardware connection or drivers.
For troubleshooting steps visit: https://docs.espressif.com/projects/esptool/en/latest/troubleshooting.html

esptool --chip esp32s3 -p /dev/cu.usbmodem1CDBD4A894401 write-flash 0x0 ./lunar/lunarcore-esp32s3.bin esptool v5.1.0 Serial port /dev/cu.usbmodem1CDBD4A894401: Connecting............. A serial exception error occurred: Could not configure port: (6, 'Device not configured') Note: This error originates from pySerial. It is likely not a problem with esptool, but with the hardware connection or drivers. For troubleshooting steps visit: https://docs.espressif.com/projects/esptool/en/latest/troubleshooting.html <!-- github-sync-id:3908751014 -->
adam commented 2026-10-05 06:05:46 +02:00
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Tried it again ...

esptool.py --chip esp32s3 -p /dev/cu.usbmodem101 write_flash 0x0 ./lunar/lunarcore-esp32s3.bin
Warning: DEPRECATED: 'esptool.py' is deprecated. Please use 'esptool' instead. The '.py' suffix will be removed in a future major release.
Warning: Deprecated: Command 'write_flash' is deprecated. Use 'write-flash' instead.
esptool v5.1.0
Connected to ESP32-S3 on /dev/cu.usbmodem101:
Chip type: ESP32-S3 (QFN56) (revision v0.2)
Features: Wi-Fi, BT 5 (LE), Dual Core + LP Core, 240MHz, Embedded PSRAM 8MB (AP_3v3)
Crystal frequency: 40MHz
USB mode: USB-Serial/JTAG
MAC: 1c:db:d4:a8:94:40

Stub flasher running.

Configuring flash size...
Flash will be erased from 0x00000000 to 0x003fffff...
Wrote 4194304 bytes (602717 compressed) at 0x00000000 in 15.0 seconds (2239.4 kbit/s).
Hash of data verified.

Hard resetting via RTS pin...

Tried it again ... esptool.py --chip esp32s3 -p /dev/cu.usbmodem101 write_flash 0x0 ./lunar/lunarcore-esp32s3.bin Warning: DEPRECATED: 'esptool.py' is deprecated. Please use 'esptool' instead. The '.py' suffix will be removed in a future major release. Warning: Deprecated: Command 'write_flash' is deprecated. Use 'write-flash' instead. esptool v5.1.0 Connected to ESP32-S3 on /dev/cu.usbmodem101: Chip type: ESP32-S3 (QFN56) (revision v0.2) Features: Wi-Fi, BT 5 (LE), Dual Core + LP Core, 240MHz, Embedded PSRAM 8MB (AP_3v3) Crystal frequency: 40MHz USB mode: USB-Serial/JTAG MAC: 1c:db:d4:a8:94:40 Stub flasher running. Configuring flash size... Flash will be erased from 0x00000000 to 0x003fffff... Wrote 4194304 bytes (602717 compressed) at 0x00000000 in 15.0 seconds (2239.4 kbit/s). Hash of data verified. Hard resetting via RTS pin... <!-- github-comment-id:3862956629 -->
adam commented 2026-10-05 06:05:47 +02:00
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rnodeconf /dev/cu.usbmodem101 --info
[00:03:08] Opening serial port /dev/cu.usbmodem101...
[00:03:12] Serial port opened, but RNode did not respond. Is a valid firmware installed?
Got invalid response while detecting device

rnodeconf /dev/cu.usbmodem101 --info [00:03:08] Opening serial port /dev/cu.usbmodem101... [00:03:12] Serial port opened, but RNode did not respond. Is a valid firmware installed? Got invalid response while detecting device <!-- github-comment-id:3862962994 -->
adam commented 2026-10-05 06:05:47 +02:00
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meshtastic --port /dev/cu.usbmodem101 --info

-->

File "/Users/xx/.local/pipx/venvs/meshtastic/lib/python3.14/site-packages/meshtastic/mesh_interface.py", line 1111, in _waitConnected
raise MeshInterface.MeshInterfaceError(
"Timed out waiting for connection completion"

meshtastic --port /dev/cu.usbmodem101 --info --> File "/Users/xx/.local/pipx/venvs/meshtastic/lib/python3.14/site-packages/meshtastic/mesh_interface.py", line 1111, in _waitConnected raise MeshInterface.MeshInterfaceError( "Timed out waiting for connection completion" <!-- github-comment-id:3862966735 -->
adam commented 2026-10-05 06:05:48 +02:00
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no connection with meshcore also

no connection with meshcore also <!-- github-comment-id:3862987746 -->
adam commented 2026-10-05 06:05:49 +02:00
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no connection with meshcore also

on it

> no connection with meshcore also on it <!-- github-comment-id:3863076927 -->
adam commented 2026-10-05 06:05:49 +02:00
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same here. with the same hardware.
I've flashed successfully but then stuck after booting.
Opening the serial after booting. I got this every 30 seconds
Backtrace: 0x4205DF53:0x3FCA0C80 0x4037C7E9:0x3FCA0CB0 0x4037E85B:0x3FCCAFA0 0x4205D77D:0x3FCCAFC0 0x4038205B:0x3FCCAFE0.

same here. with the same hardware. I've flashed successfully but then stuck after booting. Opening the serial after booting. I got this every 30 seconds `Backtrace: 0x4205DF53:0x3FCA0C80 0x4037C7E9:0x3FCA0CB0 0x4037E85B:0x3FCCAFA0 0x4205D77D:0x3FCCAFC0 0x4038205B:0x3FCCAFE0`. <!-- github-comment-id:3864563277 -->
adam commented 2026-10-05 06:05:50 +02:00
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same here. with the same hardware. I've flashed successfully but then stuck after booting. Opening the serial after booting. I got this every 30 seconds Backtrace: 0x4205DF53:0x3FCA0C80 0x4037C7E9:0x3FCA0CB0 0x4037E85B:0x3FCCAFA0 0x4205D77D:0x3FCCAFC0 0x4038205B:0x3FCCAFE0.

that's the watchdog timeout. I'm going to doublecheck the pin configuration and init code now

> same here. with the same hardware. I've flashed successfully but then stuck after booting. Opening the serial after booting. I got this every 30 seconds `Backtrace: 0x4205DF53:0x3FCA0C80 0x4037C7E9:0x3FCA0CB0 0x4037E85B:0x3FCCAFA0 0x4205D77D:0x3FCCAFC0 0x4038205B:0x3FCCAFE0`. that's the watchdog timeout. I'm going to doublecheck the pin configuration and init code now <!-- github-comment-id:3865128029 -->
adam commented 2026-10-05 06:05:51 +02:00
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Here are the concrete pin changes for XIAO ESP32S3 + Wio-SX1262 (B2B kit) that should replace the current Heltec-style hardcoded mapping:

XIAO ESP32S3 SPI pins

  • SCK = GPIO7
  • MISO = GPIO8
  • MOSI = GPIO9

Wio-SX1262 (B2B) control pins

  • NSS/CS = GPIO41
  • DIO1 = GPIO39
  • RESET = GPIO42
  • BUSY = GPIO40
  • (optional) ANT_SW = GPIO38

The current firmware appears to assume a different board pinout (typical Heltec-style: NSS=8, SCK=9, MOSI=10, MISO=11, RST=12, BUSY=13, DIO1=14). On XIAO+Wio these lines are not wired that way, so early init can fail (lots of .unwrap()), or attaching DIO1 IRQ to the wrong/floating pin can cause an interrupt storm → watchdog reset, which looks like “doesn’t boot”.

Suggestion: add a board_xiao_wio profile/feature flag and move all pin mapping into a single pins module, plus avoid .unwrap() in early boot and only subscribe DIO1 IRQ after radio init succeeds.

Here are the concrete pin changes for **XIAO ESP32S3 + Wio-SX1262 (B2B kit)** that should replace the current Heltec-style hardcoded mapping: ### XIAO ESP32S3 SPI pins - SCK = GPIO7 - MISO = GPIO8 - MOSI = GPIO9 ### Wio-SX1262 (B2B) control pins - NSS/CS = GPIO41 - DIO1 = GPIO39 - RESET = GPIO42 - BUSY = GPIO40 - (optional) ANT_SW = GPIO38 The current firmware appears to assume a different board pinout (typical Heltec-style: NSS=8, SCK=9, MOSI=10, MISO=11, RST=12, BUSY=13, DIO1=14). On XIAO+Wio these lines are not wired that way, so early init can fail (lots of `.unwrap()`), or attaching DIO1 IRQ to the wrong/floating pin can cause an interrupt storm → watchdog reset, which looks like “doesn’t boot”. Suggestion: add a `board_xiao_wio` profile/feature flag and move all pin mapping into a single `pins` module, plus avoid `.unwrap()` in early boot and only subscribe DIO1 IRQ after radio init succeeds. <!-- github-comment-id:3868781541 -->
adam commented 2026-10-05 06:05:51 +02:00
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Thank You very much for your detailed instructions. I ask myself: How exactly shall i do this bunch of changes? Shall i clone the repo and make changes there and built it afterwards?

Thank You very much for your detailed instructions. I ask myself: How exactly shall i do this bunch of changes? Shall i clone the repo and make changes there and built it afterwards? <!-- github-comment-id:3885870313 -->
adam commented 2026-10-05 06:05:52 +02:00
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They are not confirmed, it's my assumption. Yes, I think you need to clone this repo, create a new branch, implement, compile. Once it works, you can do a PR.

They are not confirmed, it's my assumption. Yes, I think you need to clone this repo, create a new branch, implement, compile. Once it works, you can do a PR. <!-- github-comment-id:3886053274 -->
adam commented 2026-10-05 06:05:53 +02:00
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Doesnt work with heltec v3 either. im giving up to fix the stuff...

Doesnt work with heltec v3 either. im giving up to fix the stuff... <!-- github-comment-id:3952920463 -->
adam commented 2026-10-05 06:05:53 +02:00
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I am using this XIAO ESP32S3 & Wio-SX1262 Kit kit https://thepihut.com/products/xiao-esp32s3-wio-sx1262-kit-for-meshtastic-lora?variant=53799857422721

And I get this output

[15:36:51]I (312) esp_image: segment 3: paddr=000e90cc vaddr=3fc9ecb0 sizeESP-ROM:esp32s3-20210327
[15:36:51]Build:Mar 27 2021
[15:36:51]rst:0x15 (USB_UART_CHIP_RESET),boot:0x2a (SPI_FAST_FLASH_BOOT)
[15:36:51]Saved PC:0x4201dfbe
[15:36:51]SPIWP:0xee
[15:36:51]mode:DIO, clock div:2
[15:36:51]load:0x3fce2820,len:0x158c
[15:36:51]load:0x403c8700,len:0xd24
[15:36:51]load:0x403cb700,len:0x2f34
[15:36:51]entry 0x403c8924
[15:36:51]I (27) boot: ESP-IDF v5.5.1-838-gd66ebb86d2e 2nd stage bootloader
[15:36:51]I (27) boot: compile time Nov 26 2025 12:27:56
[15:36:51]I (28) boot: Multicore bootloader
[15:36:51]I (29) boot: chip revision: v0.2
[15:36:51]I (32) boot: efuse block revision: v1.4
[15:36:51]I (35) boot.esp32s3: Boot SPI Speed : 40MHz
[15:36:51]I (39) boot.esp32s3: SPI Mode       : DIO
[15:36:51]I (43) boot.esp32s3: SPI Flash Size : 4MB
[15:36:51]I (47) boot: Enabling RNG early entropy source...
[15:36:51]I (51) boot: Partition Table:
[15:36:51]I (54) boot: ## Label            Usage          Type ST Offset   Length
[15:36:51]I (60) boot:  0 nvs              WiFi data        01 02 00009000 00006000
[15:36:51]I (66) boot:  1 phy_init         RF data          01 01 0000f000 00001000
[15:36:51]I (73) boot:  2 factory          factory app      00 00 00010000 003f0000
[15:36:52]I (80) boot: End of partition table
[15:36:52]I (83) esp_image: segment 0: paddr=00010020 vaddr=3c0b0020 size=2a440h (173120) map
[15:36:52]I (133) esp_image: segment 1: paddr=0003a468 vaddr=3fc99100 size=05bb0h ( 23472) load
[15:36:52]I (140) esp_image: segment 2: paddr=00040020 vaddr=42000020 size=a90a4h (692388) map
[15:36:52]I (310) esp_image: segment 3: paddr=000e90cc vaddr=3fc9ecb0 size=04248h ( 16968) load
[15:36:52]I (316) esp_image: segment 4: paddr=000ed31c vaddr=40374000 size=150e4h ( 86244) load
[15:36:52]I (341) esp_image: segment 5: paddr=00102408 vaddr=600fe010 size=00004h (     4) load
[15:36:52]I (351) boot: Loaded app from partition at offset 0x10000
[15:36:52]I (352) boot: Disabling RNG early entropy source...
[15:36:52]I (361) cpu_start: Multicore app
[15:36:52]I (371) cpu_start: Pro cpu start user code
[15:36:52]I (371) cpu_start: cpu freq: 240000000 Hz
[15:36:52]I (372) cpu_start: Application information:
[15:36:52]I (374) cpu_start: Project name:     libespidf
[15:36:52]I (379) cpu_start: App version:      v1.1.0-dirty
[15:36:52]I (385) cpu_start: Compile time:     Feb  6 2026 22:33:34
[15:36:52]I (391) cpu_start: ELF file SHA256:  000000000...
[15:36:52]I (396) cpu_start: ESP-IDF:          v5.2.1
[15:36:52]I (401) cpu_start: Min chip rev:     v0.0
[15:36:52]I (406) cpu_start: Max chip rev:     v0.99 
[15:36:52]I (411) cpu_start: Chip rev:         v0.2
[15:36:52]I (415) heap_init: Initializing. RAM available for dynamic allocation:
[15:36:52]I (423) heap_init: At 3FCA7768 len 00041FA8 (263 KiB): RAM
[15:36:52]I (429) heap_init: At 3FCE9710 len 00005724 (21 KiB): RAM
[15:36:52]I (435) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
[15:36:52]I (441) heap_init: At 600FE014 len 00001FD4 (7 KiB): RTCRAM
[15:36:52]I (448) spi_flash: detected chip: gd
[15:36:52]I (451) spi_flash: flash io: dio
[15:36:52]W (455) spi_flash: Detected size(8192k) larger than the size in the binary image header(4096k). Using the size in the binary image header.
[15:36:52]W (469) pcnt(legacy): legacy driver is deprecated, please migrate to `driver/pulse_cnt.h`
[15:36:52]W (477) i2c: This driver is an old driver, please migrate your application code to adapt `driver/i2c_master.h`
[15:36:52]W (488) timer_group: legacy driver is deprecated, please migrate to `driver/gptimer.h`
[15:36:52]I (497) sleep: Configure to isolate all GPIO pins in sleep state
[15:36:52]I (503) sleep: Enable automatic switching of GPIO sleep configuration
[15:36:52]I (511) coexist: coex firmware version: 77cd7f8
[15:36:52]I (516) coexist: coexist rom version e7ae62f
[15:36:52]I (521) main_task: Started on CPU0
[15:36:52]I (531) main_task: Calling app_main()
[15:38:06]
[15:38:06]
[15:38:06]Backtrace: 0x4205DF53:0x3FCA0C80 0x4037C7E9:0x3FCA0CB0 0x4037E85B:0x3FCCAFA0 0x4205D77D:0x3FCCAFC0 0x4038205B:0x3FCCAFE0
[15:38:06]

Interestingly the meshcore.io firmware is also not working.

Edit: I was an idiot and connected the devices by the gpio rather than the grove port

I am using this XIAO ESP32S3 & Wio-SX1262 Kit kit https://thepihut.com/products/xiao-esp32s3-wio-sx1262-kit-for-meshtastic-lora?variant=53799857422721 And I get this output ``` [15:36:51]I (312) esp_image: segment 3: paddr=000e90cc vaddr=3fc9ecb0 sizeESP-ROM:esp32s3-20210327 [15:36:51]Build:Mar 27 2021 [15:36:51]rst:0x15 (USB_UART_CHIP_RESET),boot:0x2a (SPI_FAST_FLASH_BOOT) [15:36:51]Saved PC:0x4201dfbe [15:36:51]SPIWP:0xee [15:36:51]mode:DIO, clock div:2 [15:36:51]load:0x3fce2820,len:0x158c [15:36:51]load:0x403c8700,len:0xd24 [15:36:51]load:0x403cb700,len:0x2f34 [15:36:51]entry 0x403c8924 [15:36:51]I (27) boot: ESP-IDF v5.5.1-838-gd66ebb86d2e 2nd stage bootloader [15:36:51]I (27) boot: compile time Nov 26 2025 12:27:56 [15:36:51]I (28) boot: Multicore bootloader [15:36:51]I (29) boot: chip revision: v0.2 [15:36:51]I (32) boot: efuse block revision: v1.4 [15:36:51]I (35) boot.esp32s3: Boot SPI Speed : 40MHz [15:36:51]I (39) boot.esp32s3: SPI Mode : DIO [15:36:51]I (43) boot.esp32s3: SPI Flash Size : 4MB [15:36:51]I (47) boot: Enabling RNG early entropy source... [15:36:51]I (51) boot: Partition Table: [15:36:51]I (54) boot: ## Label Usage Type ST Offset Length [15:36:51]I (60) boot: 0 nvs WiFi data 01 02 00009000 00006000 [15:36:51]I (66) boot: 1 phy_init RF data 01 01 0000f000 00001000 [15:36:51]I (73) boot: 2 factory factory app 00 00 00010000 003f0000 [15:36:52]I (80) boot: End of partition table [15:36:52]I (83) esp_image: segment 0: paddr=00010020 vaddr=3c0b0020 size=2a440h (173120) map [15:36:52]I (133) esp_image: segment 1: paddr=0003a468 vaddr=3fc99100 size=05bb0h ( 23472) load [15:36:52]I (140) esp_image: segment 2: paddr=00040020 vaddr=42000020 size=a90a4h (692388) map [15:36:52]I (310) esp_image: segment 3: paddr=000e90cc vaddr=3fc9ecb0 size=04248h ( 16968) load [15:36:52]I (316) esp_image: segment 4: paddr=000ed31c vaddr=40374000 size=150e4h ( 86244) load [15:36:52]I (341) esp_image: segment 5: paddr=00102408 vaddr=600fe010 size=00004h ( 4) load [15:36:52]I (351) boot: Loaded app from partition at offset 0x10000 [15:36:52]I (352) boot: Disabling RNG early entropy source... [15:36:52]I (361) cpu_start: Multicore app [15:36:52]I (371) cpu_start: Pro cpu start user code [15:36:52]I (371) cpu_start: cpu freq: 240000000 Hz [15:36:52]I (372) cpu_start: Application information: [15:36:52]I (374) cpu_start: Project name: libespidf [15:36:52]I (379) cpu_start: App version: v1.1.0-dirty [15:36:52]I (385) cpu_start: Compile time: Feb 6 2026 22:33:34 [15:36:52]I (391) cpu_start: ELF file SHA256: 000000000... [15:36:52]I (396) cpu_start: ESP-IDF: v5.2.1 [15:36:52]I (401) cpu_start: Min chip rev: v0.0 [15:36:52]I (406) cpu_start: Max chip rev: v0.99 [15:36:52]I (411) cpu_start: Chip rev: v0.2 [15:36:52]I (415) heap_init: Initializing. RAM available for dynamic allocation: [15:36:52]I (423) heap_init: At 3FCA7768 len 00041FA8 (263 KiB): RAM [15:36:52]I (429) heap_init: At 3FCE9710 len 00005724 (21 KiB): RAM [15:36:52]I (435) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM [15:36:52]I (441) heap_init: At 600FE014 len 00001FD4 (7 KiB): RTCRAM [15:36:52]I (448) spi_flash: detected chip: gd [15:36:52]I (451) spi_flash: flash io: dio [15:36:52]W (455) spi_flash: Detected size(8192k) larger than the size in the binary image header(4096k). Using the size in the binary image header. [15:36:52]W (469) pcnt(legacy): legacy driver is deprecated, please migrate to `driver/pulse_cnt.h` [15:36:52]W (477) i2c: This driver is an old driver, please migrate your application code to adapt `driver/i2c_master.h` [15:36:52]W (488) timer_group: legacy driver is deprecated, please migrate to `driver/gptimer.h` [15:36:52]I (497) sleep: Configure to isolate all GPIO pins in sleep state [15:36:52]I (503) sleep: Enable automatic switching of GPIO sleep configuration [15:36:52]I (511) coexist: coex firmware version: 77cd7f8 [15:36:52]I (516) coexist: coexist rom version e7ae62f [15:36:52]I (521) main_task: Started on CPU0 [15:36:52]I (531) main_task: Calling app_main() [15:38:06] [15:38:06] [15:38:06]Backtrace: 0x4205DF53:0x3FCA0C80 0x4037C7E9:0x3FCA0CB0 0x4037E85B:0x3FCCAFA0 0x4205D77D:0x3FCCAFC0 0x4038205B:0x3FCCAFE0 [15:38:06] ``` Interestingly the meshcore.io firmware is also not working. Edit: I was an idiot and connected the devices by the gpio rather than the grove port <!-- github-comment-id:4460701169 -->
adam commented 2026-10-05 06:05:54 +02:00
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With this kit it stalls on calling app_main()
https://thepihut.com/products/xiao-esp32s3-wio-sx1262-kit-for-meshtastic-lora?variant=53799857422721

[16:00:37]I (133) esp_image: segment 1: paddr=0003a468 vaddr=3fc99100 sizeESP-ROM:esp32s3-20210327
[16:00:37]Build:Mar 27 2021
[16:00:37]rst:0x15 (USB_UART_CHIP_RESET),boot:0x8 (SPI_FAST_FLASH_BOOT)
[16:00:37]Saved PC:0x4037e85e
[16:00:37]SPIWP:0xee
[16:00:37]mode:DIO, clock div:2
[16:00:37]load:0x3fce2820,len:0x158c
[16:00:37]load:0x403c8700,len:0xd24
[16:00:37]load:0x403cb700,len:0x2f34
[16:00:37]entry 0x403c8924
[16:00:37]I (27) boot: ESP-IDF v5.5.1-838-gd66ebb86d2e 2nd stage bootloader
[16:00:37]I (27) boot: compile time Nov 26 2025 12:27:56
[16:00:37]I (28) boot: Multicore bootloader
[16:00:37]I (29) boot: chip revision: v0.2
[16:00:37]I (31) boot: efuse block revision: v1.4
[16:00:37]I (35) boot.esp32s3: Boot SPI Speed : 40MHz
[16:00:37]I (39) boot.esp32s3: SPI Mode       : DIO
[16:00:37]I (43) boot.esp32s3: SPI Flash Size : 4MB
[16:00:37]I (46) boot: Enabling RNG early entropy source...
[16:00:37]I (51) boot: Partition Table:
[16:00:37]I (53) boot: ## Label            Usage          Type ST Offset   Length
[16:00:37]I (60) boot:  0 nvs              WiFi data        01 02 00009000 00006000
[16:00:37]I (66) boot:  1 phy_init         RF data          01 01 0000f000 00001000
[16:00:37]I (73) boot:  2 factory          factory app      00 00 00010000 003f0000
[16:00:37]I (79) boot: End of partition table
[16:00:37]I (83) esp_image: segment 0: paddr=00010020 vaddr=3c0b0020 size=2a440h (173120) map
[16:00:37]I (133) esp_image: segment 1: paddr=0003a468 vaddr=3fc99100 size=05bb0h ( 23472) load
[16:00:37]I (140) esp_image: segment 2: paddr=00040020 vaddr=42000020 size=a90a4h (692388) map
[16:00:37]I (310) esp_image: segment 3: paddr=000e90cc vaddr=3fc9ecb0 size=04248h ( 16968) load
[16:00:37]I (315) esp_image: segment 4: paddr=000ed31c vaddr=40374000 size=150e4h ( 86244) load
[16:00:37]I (341) esp_image: segment 5: paddr=00102408 vaddr=600fe010 size=00004h (     4) load
[16:00:37]I (351) boot: Loaded app from partition at offset 0x10000
[16:00:37]I (351) boot: Disabling RNG early entropy source...
[16:00:37]I (361) cpu_start: Multicore app
[16:00:37]I (371) cpu_start: Pro cpu start user code
[16:00:37]I (371) cpu_start: cpu freq: 240000000 Hz
[16:00:37]I (371) cpu_start: Application information:
[16:00:37]I (374) cpu_start: Project name:     libespidf
[16:00:37]I (379) cpu_start: App version:      v1.1.0-dirty
[16:00:37]I (384) cpu_start: Compile time:     Feb  6 2026 22:33:34
[16:00:37]I (391) cpu_start: ELF file SHA256:  000000000...
[16:00:37]I (396) cpu_start: ESP-IDF:          v5.2.1
[16:00:37]I (401) cpu_start: Min chip rev:     v0.0
[16:00:37]I (406) cpu_start: Max chip rev:     v0.99 
[16:00:37]I (410) cpu_start: Chip rev:         v0.2
[16:00:37]I (415) heap_init: Initializing. RAM available for dynamic allocation:
[16:00:37]I (422) heap_init: At 3FCA7768 len 00041FA8 (263 KiB): RAM
[16:00:37]I (428) heap_init: At 3FCE9710 len 00005724 (21 KiB): RAM
[16:00:37]I (435) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
[16:00:37]I (441) heap_init: At 600FE014 len 00001FD4 (7 KiB): RTCRAM
[16:00:37]I (448) spi_flash: detected chip: gd
[16:00:37]I (451) spi_flash: flash io: dio
[16:00:37]W (455) spi_flash: Detected size(8192k) larger than the size in the binary image header(4096k). Using the size in the binary image header.
[16:00:37]W (469) pcnt(legacy): legacy driver is deprecated, please migrate to `driver/pulse_cnt.h`
[16:00:37]W (477) i2c: This driver is an old driver, please migrate your application code to adapt `driver/i2c_master.h`
[16:00:37]W (488) timer_group: legacy driver is deprecated, please migrate to `driver/gptimer.h`
[16:00:37]I (497) sleep: Configure to isolate all GPIO pins in sleep state
[16:00:37]I (503) sleep: Enable automatic switching of GPIO sleep configuration
[16:00:37]I (510) coexist: coex firmware version: 77cd7f8
[16:00:37]I (516) coexist: coexist rom version e7ae62f
[16:00:37]I (521) main_task: Started on CPU0
[16:00:37]I (531) main_task: Calling app_main()
With this kit it stalls on calling `app_main()` https://thepihut.com/products/xiao-esp32s3-wio-sx1262-kit-for-meshtastic-lora?variant=53799857422721 ``` [16:00:37]I (133) esp_image: segment 1: paddr=0003a468 vaddr=3fc99100 sizeESP-ROM:esp32s3-20210327 [16:00:37]Build:Mar 27 2021 [16:00:37]rst:0x15 (USB_UART_CHIP_RESET),boot:0x8 (SPI_FAST_FLASH_BOOT) [16:00:37]Saved PC:0x4037e85e [16:00:37]SPIWP:0xee [16:00:37]mode:DIO, clock div:2 [16:00:37]load:0x3fce2820,len:0x158c [16:00:37]load:0x403c8700,len:0xd24 [16:00:37]load:0x403cb700,len:0x2f34 [16:00:37]entry 0x403c8924 [16:00:37]I (27) boot: ESP-IDF v5.5.1-838-gd66ebb86d2e 2nd stage bootloader [16:00:37]I (27) boot: compile time Nov 26 2025 12:27:56 [16:00:37]I (28) boot: Multicore bootloader [16:00:37]I (29) boot: chip revision: v0.2 [16:00:37]I (31) boot: efuse block revision: v1.4 [16:00:37]I (35) boot.esp32s3: Boot SPI Speed : 40MHz [16:00:37]I (39) boot.esp32s3: SPI Mode : DIO [16:00:37]I (43) boot.esp32s3: SPI Flash Size : 4MB [16:00:37]I (46) boot: Enabling RNG early entropy source... [16:00:37]I (51) boot: Partition Table: [16:00:37]I (53) boot: ## Label Usage Type ST Offset Length [16:00:37]I (60) boot: 0 nvs WiFi data 01 02 00009000 00006000 [16:00:37]I (66) boot: 1 phy_init RF data 01 01 0000f000 00001000 [16:00:37]I (73) boot: 2 factory factory app 00 00 00010000 003f0000 [16:00:37]I (79) boot: End of partition table [16:00:37]I (83) esp_image: segment 0: paddr=00010020 vaddr=3c0b0020 size=2a440h (173120) map [16:00:37]I (133) esp_image: segment 1: paddr=0003a468 vaddr=3fc99100 size=05bb0h ( 23472) load [16:00:37]I (140) esp_image: segment 2: paddr=00040020 vaddr=42000020 size=a90a4h (692388) map [16:00:37]I (310) esp_image: segment 3: paddr=000e90cc vaddr=3fc9ecb0 size=04248h ( 16968) load [16:00:37]I (315) esp_image: segment 4: paddr=000ed31c vaddr=40374000 size=150e4h ( 86244) load [16:00:37]I (341) esp_image: segment 5: paddr=00102408 vaddr=600fe010 size=00004h ( 4) load [16:00:37]I (351) boot: Loaded app from partition at offset 0x10000 [16:00:37]I (351) boot: Disabling RNG early entropy source... [16:00:37]I (361) cpu_start: Multicore app [16:00:37]I (371) cpu_start: Pro cpu start user code [16:00:37]I (371) cpu_start: cpu freq: 240000000 Hz [16:00:37]I (371) cpu_start: Application information: [16:00:37]I (374) cpu_start: Project name: libespidf [16:00:37]I (379) cpu_start: App version: v1.1.0-dirty [16:00:37]I (384) cpu_start: Compile time: Feb 6 2026 22:33:34 [16:00:37]I (391) cpu_start: ELF file SHA256: 000000000... [16:00:37]I (396) cpu_start: ESP-IDF: v5.2.1 [16:00:37]I (401) cpu_start: Min chip rev: v0.0 [16:00:37]I (406) cpu_start: Max chip rev: v0.99 [16:00:37]I (410) cpu_start: Chip rev: v0.2 [16:00:37]I (415) heap_init: Initializing. RAM available for dynamic allocation: [16:00:37]I (422) heap_init: At 3FCA7768 len 00041FA8 (263 KiB): RAM [16:00:37]I (428) heap_init: At 3FCE9710 len 00005724 (21 KiB): RAM [16:00:37]I (435) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM [16:00:37]I (441) heap_init: At 600FE014 len 00001FD4 (7 KiB): RTCRAM [16:00:37]I (448) spi_flash: detected chip: gd [16:00:37]I (451) spi_flash: flash io: dio [16:00:37]W (455) spi_flash: Detected size(8192k) larger than the size in the binary image header(4096k). Using the size in the binary image header. [16:00:37]W (469) pcnt(legacy): legacy driver is deprecated, please migrate to `driver/pulse_cnt.h` [16:00:37]W (477) i2c: This driver is an old driver, please migrate your application code to adapt `driver/i2c_master.h` [16:00:37]W (488) timer_group: legacy driver is deprecated, please migrate to `driver/gptimer.h` [16:00:37]I (497) sleep: Configure to isolate all GPIO pins in sleep state [16:00:37]I (503) sleep: Enable automatic switching of GPIO sleep configuration [16:00:37]I (510) coexist: coex firmware version: 77cd7f8 [16:00:37]I (516) coexist: coexist rom version e7ae62f [16:00:37]I (521) main_task: Started on CPU0 [16:00:37]I (531) main_task: Calling app_main() ``` <!-- github-comment-id:4460887664 -->
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adam (Adam Wojcieszonek)
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Reference: adam/lunarcore#2